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参数资料
| 型号： | MAX1247AEEE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SERIAL 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 133k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 667mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；4 个单端，双极；2 个差分，单极；2 个差分，双极 |
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
______________________________________________________________________________________
11
BIT
NAME
DESCRIPTION
7(MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
6
SEL2
These three bits select which of the four channels are used for the conversion (Tables 2 and 3).
5
SEL1
4
SEL0
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1
PD1
Selects clock and power-down modes.
0(LSB)
PD0
PD1
PD0
Mode
0
Full power-down
0
1
Fast power-down
1
0
Internal clock mode
1
External clock mode
Table 1. Control-Byte Format
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
tACQ = 9 x (RS + RIN) x 16pF
where RIN = 9k
, RS = the source impedance of the
input signal, and tACQ is never less than 1.5s. Note
that source impedances below 1k
do not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01F
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to VDD and AGND, allow the channel input pins to swing
from AGND - 0.3V to VDD + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD by more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 4mA.
How to Start a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1246/MAX1247’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX1246/MAX1247 are compatible with SPI/
QSPI and Microwire devices. For SPI, select the
correct clock polarity and sampling edge in the SPI
control registers: set CPOL = 0 and CPHA = 0. Micro-
wire, SPI, and QSPI all transmit a byte and receive a
byte at the same time. Using the Typical Operating
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(MSB)
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
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