参数资料
型号: MAX1249AEEE+T
厂商: Maxim Integrated Products
文件页数: 22/24页
文件大小: 0K
描述: IC ADC 10BIT SERIAL 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 10
采样率(每秒): 133k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 667mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
输入数目和类型: 4 个单端,单极;4 个单端,双极;2 个差分,单极;2 个差分,双极
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________
7
NAME
FUNCTION
1
VDD
Positive Supply Voltage
2–5
CH0–CH3
Sampling Analog Inputs
PIN
6
COM
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
7
SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1249 down; otherwise, the
devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compen-
sation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
12
DOUT
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
11
DGND
Digital Ground
9
REFADJ
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.
8
VREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.
16
SCLK
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
15
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
14
DIN
Serial Data Input. Data is clocked in at SCLK’s rising edge.
13
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the
A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
______________________________________________________________Pin Description
VDD
6k
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6k
DOUT
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
VDD
6k
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6k
DOUT
a) VOH to High-Z
b) VOL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
10
AGND
Analog Ground
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