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参数资料
| 型号： | MAX1267ACEG |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封装： | 0.150 INCH, 0.025 INCH PITCH, MO-137, QSOP-24 |
| 文件页数： | 7/19页 |
| 文件大小： | 307K |
| 代理商： | MAX1267ACEG |
M
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________
7
Pin Description
D0
10
10
INT
11
11
RD
12
12
WR
13
13
CLK
14
14
D4
6
6
D3
7
7
D2
8
8
D1
9
9
D5
5
5
D6
4
4
1
D7
3
3
D8
2
2
D9
1
Tri-State Digital I/O Line (D0)
INT
goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If
CS
is low, a falling edge on
RD
enables the read opera-
tion on the data bus.
Active-Low Write Select. When
CS
is low in the internal acquisition mode, a rising
edge on
WR
latches in configuration data and starts an acquisition plus a conver-
sion cycle. When
CS
is low in external acquisition mode, the first rising edge on
WR
ends acquisition and starts a conversion.
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock.
In internal clock mode, connect this pin to either V
DD
or GND.
Tri-State Digital I/O Line (D4)
Tri-State Digital I/O Line (D3)
Tri-State Digital I/O Line (D2)
Tri-State Digital I/O Line (D1)
Tri-State Digital I/O Line (D5)
Tri-State Digital I/O Line (D6)
Tri-State Digital I/O Line (D7)
Tri-State Digital Output (D8)
Tri-State Digital Output (D9)
GND
19
23
REFADJ
20
24
CH2
—
19
CH1
16
20
CH0
17
21
COM
18
22
CH3
—
18
CH4
—
17
CH5
—
16
CS
15
15
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01μF capacitor. When using an external reference, connect REFADJ to V
DD
to
disable the internal bandgap reference.
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5 LSB during conversion.
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Active-Low Chip Select. When
CS
is high, digital outputs (D11–D0) are high
impedance.
PIN
MAX1267
MAX1265
NAME
FUNCTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1267ACEG+ | 功能描述:模数转换器 - ADC 12-Bit 2Ch 265ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1267ACEG+T | 功能描述:模数转换器 - ADC 12-Bit 2Ch 265ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1267ACEG-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1267AEEG | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1267AEEG+ | 功能描述:模数转换器 - ADC 12-Bit 2Ch 265ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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