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参数资料
| 型号： | MAX1286EKA-T |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封装： | MO-178, SOT-23, 8 PIN |
| 文件页数： | 7/15页 |
| 文件大小： | 241K |
| 代理商： | MAX1286EKA-T |
M
150ksps, 12-Bit, 2-Channel S ingle-Ended, and
1-Channel True-Differential ADCs in S OT 23
_______________________________________________________________________________________
7
Detailed Desc ription
The MAX1286
–
MAX1289 ADCs use a successive-
approximation conversion (SAR) technique and an on-
chip track-and-hold (T/H) structure to convert an
analog signal into a 12-bit digital result.
The serial interface provides easy interfacing to micro-
processors (μPs). Figure 3 shows the simplified internal
structure for the MAX1286/MAX1287 (2 channels, sin-
gle ended) and the MAX1288/MAX1289 (1 channel,
true differential).
T rue-Differential Analog Input T /H
The equivalent circuit of Figure 4 shows the
MAX1286
–
MAX1289s
’
input architecture, which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1286/
MAX1287) or AIN+ (MAX1288/MAX1289). The negative
input capacitor is connected to GND (MAX1286/
MAX1287) or AIN- (MAX1288/MAX1289). The T/H
enters its hold mode on the falling edge of CNVST and
the difference between the sampled positive and nega-
tive input voltages is converted. The time required for
the T/H to acquire an input signal is determined by how
quickly its input capacitance is charged. If the input
signal
’
s source impedance is high, the acquisition time
lengthens, and CNVST must be held high for a longer
period of time. The acquisition time, t
ACQ
, is the maxi-
mum time needed for the signal to be acquired, plus
the power-up time. It is calculated by the following
equation:
t
ACQ
= 9 x (R
S
+ R
IN
) x 24pF + t
PWR
12-BIT
SAR
ADC
CONTROL
OSCILLATOR
INPUT SHIFT
REGISTER
T/H
REF
CNVST
SCLK
DOUT
AIN2
(AIN-)
AIN1
(AIN+)
MAX1286–MAX1289
( ) ARE FOR MAX1288/MAX1289
Figure 3. Simplified Functional Diagram
NAME
PIN
MAX1286
MAX1287
MAX1288
MAX1289
FUNCTION
1
V
DD
V
DD
Positive Supply Voltage. +2.7V to +3.6V (MAX1287/MAX1289); +4.75V to +5.25V
(MAX1286/MAX1288). Bypass with a 0.1μF capacitor to GND.
2
AIN1
AIN+
Analog Input Channel 1 (MAX1286/MAX1287) or Positive Analog Input (MAX1288/MAX1289)
3
AIN2
AIN-
Analog Input Channel 2 (MAX1286/MAX1287) or Negative Analog Input (MAX1288/MAX1289)
4
GND
GND
Ground
5
REF
REF
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1μF
capacitor to GND.
6
CNVST
CNVST
Conversion Start. A rising edge powers up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1286/MAX1287) or input polarity (MAX1288/MAX1289).
7
DOUT
DOUT
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high
impedance once data has been fully clocked out.
8
SCLK
SCLK
Serial Clock Input. Clocks out data at DOUT MSB first.
Pin Desc ription
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