参数资料
型号: MAX1289
厂商: Maxim Integrated Products, Inc.
元件分类: ADC
英文描述: 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
中文描述: 150ksps、12位、双通道单端及单通道真差分ADC
文件页数: 11/15页
文件大小: 241K
代理商: MAX1289
edges. DOUT transitions on SCLK
s falling edge
and is available in MSB-first format. Observe the
SCLK to DOUT valid timing characteristic. Clock
data into the μP on SCLK
s rising edge.
S PI and MICROWIRE Interfac e
When using an SPI (Figure 8a) or MICROWIRE inter-
face (Figures 8a and 8b), set CPOL = CPHA = 0. Two
8-bit readings are necessary to obtain the entire 12-bit
result from the ADC. DOUT data transitions on the seri-
al clock
s falling edge and is clocked into the μP on
SCLK
s rising edge. The first 8-bit data stream contains
the first 8-bits of DOUT starting with the MSB. The sec-
ond 8-bit data stream contains the remaining four result
bits. DOUT then goes high impedance.
QS PI Interfac e
Using the high-speed QSPI interface (Figure 9a) with
CPOL = 0 and CPHA = 0, the MAX1286
MAX1289
support a maximum f
SCLK
of 8MHz. One 12- to 16-bit
reading is necessary to obtain the entire 12-bit result
from the ADC. DOUT data transitions on the serial
clock
s falling edge and is clocked into the μP on
SCLK
s rising edge. The first 12 bits are the data.
DOUT then goes high impedance (Figure 9b).
PIC16 and S S P Module and
PIC17 Interfac e
The MAX1286
MAX1289 are compatible with a
PIC16/PIC17 μC, using the synchronous serial port
(SSP) module
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master. This is done by initializing its syn-
chronous serial port control register (SSPCON) and
synchronous serial port status register (SSPSTAT) to
the bit patterns shown in Tables 1 and 2.
In SPI mode, the PIC16/PIC17 μCs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings (Figure 10b)
are necessary to obtain the entire 12-bit result from the
ADC. DOUT data transitions on the serial clock
s falling
edge and is clocked into the μC on SCLK
s rising edge.
The first 8-bit data stream contains the first 8 data bits
starting with the MSB. The second data stream con-
tains the remaining bits, D3 through D0.
M
150ksps, 12-Bit, 2-Channel S ingle-Ended, and
1-Channel True-Differential ADCs in S OT 23
______________________________________________________________________________________
11
Figure 8a. SPI Connections
Figure 8b. MICROWIRE Connections
CNVST
SCLK
DOUT
I/O
SCK
MISO
V
DD
SS
SPI
MAX1286–
MAX1289
MAX1286
MAX1289
CNVST
SCLK
DOUT
I/O
SK
SI
MICROWIRE
Table 1. Detailed SSPCON Register Content
CONTROL BIT
MAX1286
MAX1289
SETTINGS
SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)
WCOL
SSPOV
Bit 7
Bit 6
X
X
Write Collision Detection Bit
Receive Overflow Detect Bit
SSPEN
Bit 5
1
Synchronous Serial Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: E nab es ser al p or and confi g ur es S C K, S D O, and S C p ns as ser al p or p ns.
CKP
SSPM3
SSPM2
SSPM1
SSPM0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects
F
CLK
= f
OSC
/ 16.
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