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参数资料
| 型号： | MAX1293ACEG |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封装： | 0.150 INCH, QSOP-24 |
| 文件页数： | 17/20页 |
| 文件大小： | 224K |
| 代理商： | MAX1293ACEG |
M
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
______________________________________________________________________________________
17
Table 6. Full-Scale and Zero-Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE
BIPOLAR MODE
COM
—
COM
Zero Scale
Negative Full Scale
Zero Scale
—
-V
REF
/2 + COM
V
REF
+ COM
V
REF
/2 + COM
Positive Full Scale
Full Scale
sion cycles, and 2 read cycles. This assumes that the
results of the last conversion are read before the next
control byte is written. Throughputs up to 300ksps can
be achieved by first writing a control word to begin the
acquisition cycle of the next conversion, and then read-
ing the results of the previous conversion from the bus
(Figure 10). This technique allows a conversion to be
completed every 16 clock cycles. Note that the switch-
ing of the data bus during acquisition or conversion
can cause additional supply noise, which may make it
difficult to achieve true 12-bit performance.
Layout, Grounding, and Bypassing
For best performance use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and don’t lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC Board ground sections with only
one starpoint (Figure 11) connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast com-
parator. Bypass V
DD
to the star ground with a network
of two parallel capacitors, 0.1μF and 4.7μF, located as
close as possible to the MAX1291/MAX1293s’ power
supply pin. Minimize capacitor lead length for best sup-
ply-noise rejection; add an attenuation resistor (5
) if
the power supply is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1291/MAX1293
are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples. Aperture delay (t
AD
) is
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution (N
bits):
SNR = (6.02
·
N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20
·
log (Signal
RMS
/ Noise
RMS
)
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PDF描述 |
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| MAX1293AEEG | 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface |
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| MAX1294BEEI | 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1293ACEG+ | 功能描述:模数转换器 - ADC 12-Bit 4Ch 250ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1293ACEG+T | 功能描述:模数转换器 - ADC 12-Bit 4Ch 250ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1293ACEG-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1293AEEG | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1293AEEG+ | 功能描述:模数转换器 - ADC 12-Bit 4Ch 250ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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