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参数资料
| 型号： | MAX1302AEUG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/31页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SRL 115KSPS 24TSSOP |
| 标准包装： | 2,500 |
| 位数： | 16 |
| 采样率（每秒）： | 115k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.11W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
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MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
12
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
AVDD1
Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD1
to AGND1 with a 0.1F capacitor.
2
CH0
Analog Input Channel 0
3
CH1
Analog Input Channel 1
4
CH2
Analog Input Channel 2
5
CH3
Analog Input Channel 3
6
CH4
Analog Input Channel 4
7
CH5
Analog Input Channel 5
8
CH6
Analog Input Channel 6
9
CH7
Analog Input Channel 7
10
CS
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the rising
edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK. When CS is high,
activity on SCLK and DIN is ignored and DOUT is high impedance.
11
DIN
Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is high,
transitions on DIN are ignored.
12
SSTRB
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that data is
ready to be read from the device. When operating in external clock mode, SSTRB is always low. SSTRB
does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.
13
SCLK
Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT. When CS
is high, transitions on SCLK are ignored.
14
DOUT
Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK transition.
When CS is high, DOUT is high impedance.
15
DGNDO
Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
16
DGND
Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
17
DVDDO
Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage. Bypass
DVDDO to DGNDO with a 0.1F capacitor.
18
DVDD
Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage. Bypass
DVDD to DGND with a 0.1F capacitor.
19
REFCAP
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD. For
internal reference operation, bypass REFCAP with a 0.01F capacitor to AGND1 (VREFCAP
≈ 4.096V).
20
REF
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an external
reference voltage from 3.800V to 4.136V to REF. For internal reference operation, bypassing REF with a
1F capacitor to AGND1 sets VREF = 4.096V ±1%.
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| MAX13030EEBE+T | 功能描述:转换 - 电压电平 6Ch High-Speed RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
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