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参数资料
| 型号： | MAX1304ECM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/37页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CH 4MSPS 48LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 位数： | 12 |
| 采样率（每秒）： | 3.65M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.82W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极 |
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MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
Reading a Conversion Result
Reading During a Conversion
Figures 7 and 8 show the interface signals to initiate a
read operation during a conversion cycle. These figures
show two channels selected for conversion. If more
channels are selected, the results are available succes-
sively at every EOC falling edge. CS can be low at all
times, low during the RD cycles, or the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC to go low. In internal clock mode, EOC
goes low within 900ns. In external clock mode, EOC
goes low on the rising edge of the 13th CLK cycle. To
read the conversion result, drive CS and RD low to
latch data to the parallel digital output bus. Bring RD
high to release the digital bus. In internal clock mode,
the next EOC falling edge occurs within 225ns. In exter-
nal clock mode, the next EOC falling edge occurs in
three CLK cycles. When the last result is available
EOLC goes low.
Reading After Conversion
Figure 9 shows the interface signals for a read operation
after a conversion with all eight channels enabled. At
the falling of EOLC, driving CS and RD low places the
first conversion result onto the parallel bus. Successive
low pulses of RD place the successive conversion
results onto the bus. When the last conversion results in
the sequence are read, additional read pulses wrap the
pointer back to the first converted result.
CONVST
CLK
CH3
TRACK
HOLD
D0–D11
SAMPLE
INSTANT
tACQ
tCNTC
tCTR
tRDH
tRTC
tACC
tRDL
tREQ
TRACK
CH7
EOC
RD
1
2
3
12
13
14
15
16
17
18
19
1
tCLK
tEOCD
tCONV
tNEXT
tEOC
tEOCD
tCLKH
tEOLCD
tCVEOLCD
tQUIET
≥ 50ns
tCLKL
EOLC
CS*
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 8. Read During Conversion—Channel 3 and Channel 7 Selected, External Clock
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________
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相关代理商/技术参数 |
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| MAX13050ASA | 功能描述:CAN 接口集成电路 CAN Transceiver w/80V Fault Protect RoHS:否 制造商:Texas Instruments 类型:Transceivers 工作电源电压:5 V 电源电流: 工作温度范围:- 40 C to + 85 C 封装 / 箱体:SOIC-8 封装:Tube |
| MAX13050ASA+ | 功能描述:CAN 接口集成电路 CAN Transceiver w/80V Fault Protect RoHS:否 制造商:Texas Instruments 类型:Transceivers 工作电源电压:5 V 电源电流: 工作温度范围:- 40 C to + 85 C 封装 / 箱体:SOIC-8 封装:Tube |
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| MAX13050ASA-T | 功能描述:CAN 接口集成电路 CAN Transceiver w/80V Fault Protect RoHS:否 制造商:Texas Instruments 类型:Transceivers 工作电源电压:5 V 电源电流: 工作温度范围:- 40 C to + 85 C 封装 / 箱体:SOIC-8 封装:Tube |
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