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| 型号： | MAX1304ECM |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with 【10V, 【5V, and 0 to +5V Analog Input Ranges |
| 中文描述： | 8-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, TQFP-48 |
| 文件页数： | 23/36页 |
| 文件大小： | 487K |
| 代理商： | MAX1304ECM |
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M
8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________
23
Reading a Conversion Result
Reading During a Conversion
Figures 7 and 8 show the interface signals to initiate a
read operation during a conversion cycle. These figures
show two channels selected for conversion. If more
channels are selected, the results are available succes-
sively at every
EOC
falling edge.
CS
can be low at all
times, low during the
RD
cycles, or the same as
RD
.
After initiating a conversion by bringing CONVST high,
wait for
EOC
to go low. In internal clock mode,
EOC
goes low within 900ns. In external clock mode,
EOC
goes low on the rising edge of the 13th CLK cycle. To
read the conversion result, drive
CS
and
RD
low to
latch data to the parallel digital output bus. Bring
RD
high to release the digital bus. In internal clock mode,
the next
EOC
falling edge occurs within 225ns. In exter-
nal clock mode, the next
EOC
falling edge occurs in
three CLK cycles. When the last result is available
EOLC
goes low.
Reading After Conversion
Figure 9 shows the interface signals for a read operation
after a conversion with all eight channels enabled. At
the falling of
EOLC
, driving
CS
and
RD
low places the
first conversion result onto the parallel bus. Successive
low pulses of
RD
place the successive conversion
results onto the bus. When the last conversion results in
the sequence are read, additional read pulses wrap the
pointer back to the first converted result.
CONVST
CLK
CH3
TRACK
HOLD
D0–D11
SAMPLE
INSTANT
t
ACQ
t
CNTC
t
CTR
t
RDH
t
RTC
t
ACC
t
RDL
t
REQ
TRACK
CH7
EOC
RD
1
2
3
12
13
14
15
16
17
18
19
1
t
CLK
t
EOCD
t
CONV
t
NEXT
t
EOC
t
EOCD
t
CLKH
t
EOLCD
t
CVEOLCD
t
QUIET
≥
50ns
t
CLKL
EOLC
CS*
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 8. Read During Conversion—Channel 3 and Channel 7 Selected, External Clock
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1304ECM/V+ | 功能描述:模数转换器 - ADC 12-Bit 8Ch 1.075Msps 3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1304ECM/V+T | 功能描述:模数转换器 - ADC 12-Bit 8Ch 1.075Msps 3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1304ECM+ | 功能描述:模数转换器 - ADC 12-Bit 8Ch 1.075Msps 3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1304ECM+T | 功能描述:模数转换器 - ADC 12-Bit 8Ch 1.075Msps 3V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1304ECM-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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