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参数资料
| 型号： | MAX1317ECM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/27页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 4CH 1.4MSPS 48LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 位数： | 14 |
| 采样率（每秒）： | 1.4M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极 |
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MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
16
______________________________________________________________________________________
To write to the configuration register, pull CS and WR
low, load bits D0–D7 onto the parallel bus, and force
WR high. The data are latched on the rising edge of
WR (Figure 4). It is possible to write to the configuration
register at any point during the conversion sequence;
however, it is not active until the next convert-start sig-
nal. At power-up, write to the configuration register to
select the active channels before beginning a conver-
sion. Shutdown does not change the configuration reg-
ister. See the
Shutdown Mode and the ALLON sections
for information about using the configuration register for
power saving.
Starting a Conversion
To start a conversion using internal-clock mode, pull
CONVST low for at least the acquisition time (t1). The
T/H acquires the signal while CONVST is low, and con-
version begins on the rising edge of CONVST. An end-
of-conversion signal (EOC) pulses low when the first
result becomes available, and for each subsequent
result until the end of the conversion cycle. The end-of-
last-conversion signal (EOLC) goes low when the last
conversion result is available (Figures 5, 6, and 7).
To start a conversion using external-clock mode, pull
CONVST low for at least the acquisition time (t1). The T/H
acquires the signal while CONVST is low, and conversion
begins on the rising edge of CONVST. Apply an external
clock to CLK. To avoid T/H droop degrading the sampled
analog input signals, the first clock pulse should occur
within 10s from the rising edge of CONVST, and have a
minimum clock frequency of 100kHz. The first conversion
result is available for read on the rising edge of the 17th
clock cycle, and subsequent conversions after every third
clock cycle thereafter (Figures 5, 6, and 7).
In both internal- and external-clock modes, CONVST
must be held high until the last conversion result is
read. For best operation, the rising edge of CONVST
must be a clean, high-speed, low-jitter digital signal.
Table 3 shows the total throughput as a function of the
clock frequency and the number of channels selected
for conversion. The calculations use the nominal speed
of the internal clock (10MHz) and a 200ns CONVST
pulse width.
Table 2. Configuration Register
BIT/CHANNEL
PART NO.
STATE
D0/CH0
D1/CH1
D2/CH2
D3/CH3
D4/CH4
D5/CH5
D6/CH6
D7/CH7
ON
11111
11
1
MAX1316
MAX1320
MAX1324
OFF
00000
00
0
ON
1111
NA
MAX1317
MAX1321
MAX1325
OFF
0000
NA
ON
1
NA
MAX1318
MAX1322
MAX1326
OFF
0
NA
NA = Not applicable.
Figure 4. Write Timing
D0–D7
DATA-IN
RD
CS
WR
t2
t5
t6
t14
t15
t7
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| MAX13181EELB+ | 制造商:Maxim Integrated Products 功能描述:LINE TRANSMITTER/RCVR 1TR 1TX 1RX 10PIN UDFN - Rail/Tube |
| MAX13181EELB+T | 功能描述:RS-485接口IC Ic Txrx RS-485 +5.0V Esd RoHS:否 制造商:Texas Instruments 数据速率:250 Kbps 工作电源电压:3.3 V 电源电流:750 uA 工作温度范围:- 40 C to + 125 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| MAX13182EELB+T | 功能描述:RS-485接口IC Ic Txrx RS-485 +5.0V Esd RoHS:否 制造商:Texas Instruments 数据速率:250 Kbps 工作电源电压:3.3 V 电源电流:750 uA 工作温度范围:- 40 C to + 125 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| MAX13182EESD+ | 功能描述:RS-485接口IC Ic Txrx RS-485 +5.0V Esd RoHS:否 制造商:Texas Instruments 数据速率:250 Kbps 工作电源电压:3.3 V 电源电流:750 uA 工作温度范围:- 40 C to + 125 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| MAX13182EESD+T | 功能描述:RS-485接口IC Ic Txrx RS-485 +5.0V Esd RoHS:否 制造商:Texas Instruments 数据速率:250 Kbps 工作电源电压:3.3 V 电源电流:750 uA 工作温度范围:- 40 C to + 125 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
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