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参数资料
| 型号： | MAX13184EESD+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/18页 |
| 文件大小： | 0K |
| 描述： | IC TXRX RS-485 +5.0V ESD 14SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | RS485 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOIC |
| 包装： | 带卷 (TR) |
MAX13181E–MAX13184E
+5.0V, ±15kV ESD-Protected, Half-Duplex/
Full-Duplex, RS-485 Transceiver in DFN
4
_______________________________________________________________________________________
DRIVER SWITCHING CHARACTERISTICS—MAX13183E/MAX13184E (MAXIMUM DATA
RATE OF 16Mbps)
(VCC = +5V ±10%, TA =TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tDPLH
CL = 50pF, RL = 54
Ω, Figure 3
25
Driver Propagation Delay
tDPHL
CL = 50pF, RL = 54
Ω, Figure 3
25
ns
Driver Differential Output Rise or Fall TimetDR, tDF
CL = 50pF, RL = 54
Ω, Figure 3
15
ns
Differential Driver Output Skew
(tDPLH - tDPHL)
tDSKEW
CL = 50pF, RL = 54
Ω, Figure 3
8
ns
Maximum Data Rate
16
Mbps
Driver Enable to Output-High
tDZH
Figures 1 and 4a
50
ns
Driver Enable to Output-Low
tDZL
Figures 1 and 4b
50
ns
Driver Disable Time from Low
tDLZ
Figures 1 and 4b
50
ns
Driver Disable Time from High
tDHZ
Figures 1 and 4a
50
ns
Driver Enable from Shutdown to Output
High
tDZH (SHDN) Figures 1 and 4a (MAX13184E)
2200
ns
Driver Enable from Shutdown to Output
Low
tDZL (SHDN)
Figures 1 and 4b (MAX13184E)
2200
ns
Time to Shutdown
tSHDN
(MAX13184E)
50
200
600
ns
RECEIVER SWITCHING CHARACTERISTICS
(VCC = +5V ±10%, TA =TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tRPLH
40
75
Receiver Propagation Delay
tRPHL
CL = 15pF, Figure 5
40
75
ns
Receiver Output Skew (tRPLH - tRPHL)tRSKEW
CL = 15pF, Figure 5
8
ns
Maximum Data Rate
16
Mbps
Receiver Enable to Output Low
tRZL
(MAX13182E/MAX13184E)
Figures 2 and 6
50
ns
Receiver Enable to Output High
tRZH
(MAX13182E/MAX13184E)
Figures 2 and 6
50
ns
Receiver Disable Time from Low
tRLZ
(MAX13182E/MAX13184E)
Figures 2 and 6
50
ns
Receiver Disable Time from High
tRHZ
(MAX13182E/MAX13184E)
Figures 2 and 6
50
ns
Receiver Enable from Shutdown to
Output High
tRZH (SHDN)
(MAX13182E/MAX13184E)
Figures 2 and 6
2200
ns
Receiver Enable from Shutdown to
Output Low
tRZL (SHDN)
(MAX13182E/MAX13184E)
Figures 2 and 6
2200
ns
Note 1: All currents into the device are positive. All currents out of the device are negative. All voltages are referred to device ground,
unless otherwise noted. DFN devices are production tested at +25°C. Overtemperature limits are guaranteed by design.
Note 2: ΔVOD and ΔVOC are the changes in VOD and VOC, respectively, when the DI input changes state.
Note 3: The short-circuit output current applies to peak current just prior to foldback current limiting. The short-circuit foldback output
current applies during current limiting to allow a recovery from bus contention.
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