参数资料
型号: MAX13444EASA+T
厂商: Maxim Integrated Products
文件页数: 6/18页
文件大小: 0K
描述: IC TXRX J1708 HALF DUPLEX 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 收发器
驱动器/接收器数: 1/1
规程: RS422,RS485
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
MAX13442E/MAX13443E/MAX13444E
±15kV ESD-Protected, ±80V Fault-Protected,
Fail-Safe RS-485/J1708 Transceivers
14
______________________________________________________________________________________
VCC
TIMER
DE
(HOT SWAP)
15
μs
100
μA
M1
M2
5.6k
Ω
2mA
Figure 10. Simplified Structure of the Driver Enable Pin (DE)
Hot-Swap Capability
Hot-Swap Inputs
Inserting circuit boards into a hot, or powered, back-
plane may cause voltage transients on DE, RE, and
receiver inputs A and B that can lead to data errors. For
example, upon initial circuit board insertion, the proces-
sor undergoes a power-up sequence. During this period,
the high-impedance state of the output drivers makes
them unable to drive the MAX13442E/MAX13443E/
MAX13444E enable inputs to a defined logic level.
Meanwhile, leakage currents of up to 10A from the
high-impedance output, or capacitively coupled noise
from VCC or GND, could cause an input to drift to an
incorrect logic state. To prevent such a condition from
occurring, the MAX13442E/MAX13443E/MAX13444E
feature hot-swap input circuitry on DE, and RE to guard
against unwanted driver activation during hot-swap sit-
uations. The MAX13444E has hot-swap input circuitry
only on RE. When VCC rises, an internal pulldown (or
pullup for RE) circuit holds DE low for at least 10s, and
until the current into DE exceeds 200A. After the initial
power-up sequence, the pulldown circuit becomes
transparent, resetting the hot-swap tolerable input.
Hot-Swap Input Circuitry
At the driver-enable input (DE), there are two NMOS
devices, M1 and M2 (Figure 10). When VCC ramps from
zero, an internal 15s timer turns on M2 and sets the
SR latch, which also turns on M1. Transistors M2, a
2mA current sink, and M1, a 100A current sink, pull
DE to GND through a 5.6k
Ω resistor. M2 pulls DE to the
disabled state against an external parasitic capaci-
tance up to 100pF that may drive DE high. After 15s,
the timer deactivates M2 while M1 remains on, holding
DE low against three-state leakage currents that may
drive DE high. M1 remains on until an external current
source overcomes the required input current. At this
time, the SR latch resets M1 and turns off. When M1
turns off, DE reverts to a standard, high-impedance
CMOS input. Whenever VCC drops below 1V, the input
is reset.
A complementary circuit for RE uses two PMOS
devices to pull RE to VCC.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
Ω
RD
1.5k
Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 9a. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
AMPERES
Figure 9b. Human Body Model Current Waveform
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MAX13442EASA+T IC TXRX RS485 HALF DUPLEX 8-SOIC
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