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参数资料
| 型号： | MAX1364MEUB+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/25页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MON 12BIT 4CH 10-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 133k |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 444.4mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-µMAX |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；4 个单端，双极；2 个差分，单极；2 个差分，双极 |
where RSOURCE is the analog-input source impedance,
RIN = 2.5kΩ, and CIN = 22pF. For internal clock mode,
tACQ = 1.5 / fSCL, and for external clock mode tACQ =
2 / fSCL.
Analog-Input Bandwidth
The MAX1363/MAX1364 feature input-tracking circuitry
with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals from aliasing into the frequency band of
interest, use anti-aliasing filtering.
Analog-Input Range and Protection
Internal protection diodes clamp the analog inputs to VDD
and GND. These diodes allow the analog inputs to swing
from (GND - 0.3V) to (VDD + 0.3V) without causing dam-
age to the device. For accurate conversions, the inputs
must remain within 50mV below GND or above VDD.
Single-Ended/Differential Input
The SE/
DIF of the configuration byte configures the
MAX1363/MAX1364 analog-input circuitry for single-
ended or differential input. In single-ended mode (SE/
DIF
= 1), the digital conversion results are the difference
between the analog input selected by CS[3:0] and GND.
In differential mode (SE/
DIF = 0), the digital conversion
results are the difference between the plus and the minus
analog inputs selected by CS[3:0] (see Tables 5 and 6).
Unipolar/Bipolar
Unipolar mode sets the differential input range from 0 to
VREF. A negative differential analog input in unipolar
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to ±VREF / 2. The digital output code is binary in unipo-
lar mode and two’s complement in bipolar mode. (See
the
Transfer Functions section.)
In single-ended mode the MAX1363/MAX1364 always
operate in unipolar mode. The analog inputs are inter-
nally referenced to GND with a full-scale input range
from 0 to VREF (Table 7).
Reference
SEL[2:0] of the setup byte controls the reference and
the AIN3/REF configuration. When AIN3/REF is config-
ured as a reference input or reference output (SEL1 =
1), differential conversions on AIN3/REF appear as if
AIN3/REF is connected to GND. A single-ended conver-
sion in scan mode on AIN3/REF is ignored by an internal
limiter that sets the highest available channel at AIN2.
Internal Reference
The internal reference is 2.048V for the MAX1363 and
4.096V for the MAX1364. SEL1 of the setup byte con-
trols whether AIN3/REF is used for an analog input or a
reference. Decouple AIN3/REF to GND with a 0.1F
capacitor and a 2kΩ resistor in series with the capaci-
tor. When AIN3/REF is configured as an internal refer-
ence output (SEL[1:0] = 11). See the
Typical Operating
Circuit. Once powered up, the reference remains on
until reconfigured. Do not use the reference to supply
current for external circuitry.
External Reference
The external reference ranges from 1V to VDD. For max-
imum conversion accuracy, the reference must deliver
40A and have an impedance of 500Ω or less. For
noisy or high-output-impedance references, insert a
0.1F bypass capacitor to GND as close to AIN3/REF
as possible.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s
INT/EXT clock bit determines the clock
mode. At power-up, the MAX1363/MAX1364 default to
internal clock mode (
INT/EXT clock = 0).
Internal Clock
See the
Configuration/Setup Bytes (Write Cycle) section.
In internal clock mode (CLK = 0), the MAX1363/
MAX1364 use an internal oscillator for the conversion
clock. The MAX1363/MAX1364 begin tracking the analog
input after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While con-
verting, the MAX1363/MAX1364 hold SCL low (clock
stretching). After completing the conversion, the results
are stored in internal memory. For scan-mode configura-
tions with multiple conversions (see the
Scan Modes sec-
tion), all conversions happen in succession with each
additional result stored in memory. Once all conversions
are complete, the MAX1363/MAX1364 release SCL,
allowing it to go high. The master can now clock the
results out in the same order as the scan conversion.
The converted results are read back in a FIFO
sequence. If AIN3/REF is configured as a reference
input or output, AIN3/REF is excluded from multichan-
nel scan. If reading continues past the final result
stored in memory, the pointer wraps around and points
to the first result. Only the current conversion results are
read from memory. The MAX1363/MAX1364 must be
addressed with a read command to obtain new conver-
sion results.
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________
11
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