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| 型号： | MAX1441GUP/V+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 24/41页 |
| 文件大小： | 0K |
| 描述： | IC PROXMITY SENSOR 2CH 20-TSSOP |
| 其它有关文件： | Automotive Product Guide |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 74 |
| 类型： | 触控式传感器 |
| 输入类型： | 数字 |
| 输出类型： | 数字 |
| 接口： | JTAG，串行 |
| 电流 - 电源： | 100µA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
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MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
30
Table 11. Special-Function Register Bit Description (continued)
REGISTER
DESCRIPTION
CO1 (10h, 01h)
Channel 1 Capacitance Offset Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
Unrestricted read/write.
CO1[5:0]
Channel 1 Capacitance Offset Bits [5:0]. These bits select the amount of capacitance compensation
to be applied. Capacitance can be adjusted in a 1pF increment up to 63pF.
CO1[7:6]
Reserved. Read returns 0.
CO2 (11h, 01h)
Channel 2 Capacitance Offset Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
Unrestricted read/write.
CO2[5:0]
Channel 2 Capacitance Offset Bits [5:0]. These bits select the amount of capacitance compensation
to be applied. Capacitance can be adjusted in a 1pF increment up to 63pF.
CO2[7:6]
Reserved. Read returns 0.
DSB (12h, 01h)
Standby State Conversion Rate Divider Register (8-Bit Register)
Initialization
This register is cleared to 01h on all forms of reset.
Read/Write Access
Unrestricted read/write.
DSB[4:0]
Standby State Conversion Rate Divider Bits [4:0]. These bits set the conversion rate divider for both
channels 1 and 2 in the standby state. The conversion rate is reduced by DSB[4:0].
DSB[7:5]
Reserved. Read returns 0.
SSB2 (13h, 01h)
Channel 2 Standby State Conversion Rate Subdivider Register (8-Bit Register)
Initialization
This register is cleared to 01h on all forms of reset.
Read/Write Access
Unrestricted read/write.
SSB2[4:0]
Channel 2 Standby State Conversion Rate Divider Bits [4:0]. These bits set the additional channel 2
conversion rate divider that is applied, in addition to the DSB divide ratio in the standby state. The con-
version rate for channel 2 is divided by DSB[4:0] x SSB2[4:0].
SSB2[7:5]
Reserved. Read returns 0.
AFEIE (14h, 01h)
AFE Interrupt Enable Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
Unrestricted read/write.
AFEIE.0–EDR1
CH1 Data Ready Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when the IDR1
bit is set to 1. Clearing this bit to 0 disables an interrupt from generating.
AFEIE.1–EDR2
CH2 Data Ready Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when the IDR2
bit is set to 1. Clearing this bit to 0 disables an interrupt from generating.
AFEIE.2–EIWUP1
CH1 Wake-Up Event Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when
EIWUP1 = 1. Clearing this bit to 0 disables an interrupt from generating.
AFEIE.3–EIWUP2
CH2 Wake-Up Event Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when
EIWUP2 = 1. Clearing this bit to 0 disables an interrupt from generating.
AFEIE[7:4]
Reserved. Read returns 0.
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