参数资料
型号: MAX1446GHJ+T
厂商: Maxim Integrated Products
文件页数: 6/20页
文件大小: 0K
描述: IC ADC 10BIT 60MSPS 3V 32-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 10
采样率(每秒): 60M
数据接口: 并联
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP(5x5)
包装: 带卷 (TR)
输入数目和类型: 2 个单端,双极;1 个差分,双极
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
14
______________________________________________________________________________________
samples at the falling edge of the input clock. Output
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal refer-
ence provides a VDD/2 output voltage for level shifting
purposes. The input is buffered and then split to a volt-
age follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associ-
ated with high-speed op amps. The user may select the
RISO and CIN values to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an RISO of 50Ω is placed before the capaci-
tive load to prevent ringing and oscillation. The 22pF
CIN capacitor acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1446 for
optimum performance. Connecting the transformer’s
center tap to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1446 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
Single-Ended AC-Coupled
Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion. The MAX4108 op amp provides high speed, high
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
Buffered External Reference Drives
Multiple ADCs
Multiple-converter systems based on the MAX1446 are
well suited for use with a common reference voltage.
The REFIN pin of those converters can be connected
directly to an external reference source. A precision
bandgap reference like the MAX6062 generates an
external DC level of 2.048V (Figure 10), and exhibits a
noise voltage density of 150n
√Hz. Its output passes
through a 1-pole lowpass filter (with 10Hz cutoff fre-
quency) to the MAX4250, which buffers the reference
before its output is applied to a second 10Hz lowpass
N - 6
N
N - 5
N + 1
N - 4
N + 2
N - 3
N + 3
N - 2
N + 4
N - 1
N + 5
N
N + 6
N + 1
5.5 CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
tDO
Figure 6. System and Output Timing Diagram
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