参数资料
型号: MAX14541EAXK+T
厂商: Maxim Integrated Products
文件页数: 7/8页
文件大小: 0K
描述: IC ESD PROTECTOR 3CH SC70-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
电极标记: 3 通道阵列 - 单向
安装类型: 表面贴装
封装/外壳: 6-TSSOP(5 引线),SC-88A,SOT-353
供应商设备封装: SC-70-5
包装: 标准包装
产品目录页面: 1424 (CN2011-ZH PDF)
其它名称: MAX14541EAXK+TDKR
3-Channel, Low-Leakage ESD Protector
__________Layout Recommendations
Proper circuit-board layout is critical to suppress ESD-
induced line transients (see Figure 6). The MAX14541E
clamps to 100V; however, with improper layout, the
voltage spike at the device can be much higher. A lead
inductance of 10nH with a 45A current spike results in an
additional 450V spike on the protected line. It is essential
that the layout of the PCB follows these guidelines:
V CC
L1
PROTECTED LINE
NEGATIVE ESD
L2
1) Minimize trace length between the connector or input
terminal, I/O_, and the protected signal line.
2) Use separate planes for power and ground to reduce
parasitic inductance and to reduce the impedance to
CURRENT
PULSE
PATH TO
GROUND
D1
I/O_
V C
PROTECTED
CIRCUIT
the power rails for shunted ESD current.
3) Ensure short low-inductance ESD transient return
paths to GND and V CC .
D2
4) Minimize conductive power and ground loops.
5) Do not place critical signals near the edge of the
PCB.
6) Bypass V CC to GND with a low-ESR ceramic capaci-
tor as close as possible to V CC .
GND
Figure 6. Layout Considerations
L3
7) Bypass the supply of the protected device to GND
with a low-ESR ceramic capacitor as close as pos-
sible to the supply pin.
___________________________________________________Typical Application Circuit
I/0 LINE
I/0
0.1 μ F
V CC
I/0_
0.1 μ F
V CC
PROTECTED
CIRCUIT
MAX14541E
_______________________________________________________________________________________
7
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