参数资料
型号: MAX14801CCM+T
厂商: Maxim Integrated Products
文件页数: 16/20页
文件大小: 0K
描述: IC SWITCH SPST 48LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
功能: 开关
电路: 单刀单掷
导通状态电阻: 48 欧姆
电压电源: 单电源
电压 - 电源,单路/双路(±): 2.7 V ~ 5.5 V
电流 - 电源: 5µA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
MAX14802/MAX14803/MAX14803A
Low-Charge Injection, 16-Channel,
High-Voltage Analog Switches
5
Maxim Integrated
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.5V, VPP = +40V to VNN + 200V, VNN = -40V to -160V, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC TIMING (Figure 1)
VDD = +5V ±10%
20
CLK Frequency
fCLK
VDD = +3V ±10%
10
MHz
VDD = +5V ±10%
10
DIN to CLK Setup Time
tDS
VDD = +3V ±10%
16
ns
VDD = +5V ±10%
3
DIN to CLK Hold Time
tDH
VDD = +3V ±10%
3
ns
VDD = +5V ±10%
36
CLK to LE Setup Time
tCS
VDD = +3V ±10%
65
ns
VDD = +5V ±10%
14
LE Low-Pulse Width
tWL
VDD = +3V ±10%
22
ns
VDD = +5V ±10%
20
CLR High-Pulse Width
tWC
VDD = +3V ±10%
40
ns
VDD = +5V ±10%
50
CLK Rise and Fall Times
tR, tF
VDD = +3V ±10%
50
ns
VDD = +5V ±10%
6
42
CLK to DOUT Delay
tDO
VDD = +3V ±10%
12
80
ns
Note 2: All devices are 100% tested at TA = +70°C. Limits over the operating temperature range are guaranteed by design and
characterization.
Note 3: The analog signal input VCOM_ and VNO_ must satisfy VNN ≤ (VCOM_, VNO_) ≤ VPP, or remain unconnected during power-up
and power-down.
Note 4: Guaranteed by characterization; not production tested.
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