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参数资料
| 型号： | MAX148BCPP+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/23页 |
| 文件大小： | 0K |
| 描述： | IC ADC SRL 8CH 10BIT LP 20-DIP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 18 |
| 位数： | 10 |
| 采样率（每秒）： | 133k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 889mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 20-PDIP |
| 包装： | 管件 |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
14
Table 4. Typical Power-Up Delay Times
the control byte (the PD0 bit) is clocked into DIN. The
start bit is defined as follows:
The first high bit clocked into DIN with CS low any time
the converter is idle; e.g., after VDD is applied.
OR
The first high bit clocked into DIN after bit 3 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized
as a start bit; the current conversion is terminated, and
a new one is started.
The fastest the MAX148/MAX149 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 11a shows the serial-interface timing necessary
to perform a conversion every 15 SCLK cycles in exter-
nal clock mode. If CS is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (FCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a FC can drive the
MAX148/MAX149. Figure 11b shows the serial-interface
timing necessary to perform a conversion every 16 SCLK
cycles in external clock mode.
Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX148/MAX149 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies stabi-
lize, the internal reset time is 10Fs, and no conversions
should be performed during this phase. SSTRB is high
on power-up and, if CS is low, the first logical 1 on DIN is
interpreted as a start bit. Until a conversion takes place,
DOUT shifts out zeros. Also see Table 4.
Reference-Buffer Compensation
In addition to its shutdown function, SHDN selects inter-
nal or external compensation. The compensation affects
both power-up time and maximum conversion speed.
The 100kHz minimum clock rate is limited by droop on
the sample-and-hold and is independent of the compen-
sation used.
Unconnect SHDN to select external compensation. The
Typical Operating Circuit uses a 4.7FF capacitor at VREF.
A 4.7FF value ensures reference-buffer stability and
allows converter operation at the 2MHz full clock speed.
External compensation increases power-up time (see the
Choosing Power-Down Mode section and Table 4).
Pull SHDN high to select internal compensation. Internal
compensation requires no external capacitor at VREF
and allows for the shortest power-up times. The maxi-
mum clock rate is 2MHz in internal clock mode and
400kHz in external clock mode.
Choosing Power-Down Mode
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down mode or fast power-down mode via bits 1
and 0 of the DIN control byte with SHDN high or uncon-
nected (Tables 1 and 5). In both software power-down
modes, the serial interface remains operational, but the
ADC does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current to
2FA (typ). Fast power-down mode turns off all circuitry
except the bandgap reference. With fast power-down
mode, the supply current is 30FA. Power-up time can be
shortened to 5Fs in internal compensation mode.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
REFERENCE
BUFFER
REFERENCE-
BUFFER
COMPENSATION
MODE
VREF
CAPACITOR
(F)
POWER-DOWN
MODE
POWER-UP DELAY
(s)
MAXIMUM
SAMPLING RATE
(ksps)
Enabled
Internal
—
Fast
5
26
Enabled
Internal
—
Full
300
26
Enabled
External
4.7
Fast
See Figure 14c
133
Enabled
External
4.7
Full
See Figure 14c
133
Disabled
—
Fast
2
133
Disabled
—
Full
2
133
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX148BCPP+ | 功能描述:模数转换器 - ADC 10-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX148BEAP | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX148BEAP+ | 功能描述:模数转换器 - ADC 10-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX148BEAP+T | 功能描述:模数转换器 - ADC 10-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX148BEAP-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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