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参数资料
| 型号： | MAX15005BAUE/V+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/27页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM 16-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 96 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 81.5% |
| 电源电压： | 4.5 V ~ 40 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 是 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
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MAX15004A/B/MAX15005A/B
4.5V to 40V Input Automotive
Flyback/Boost/SEPIC Power-Supply Controllers
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
—
NAME
IN
ON/ OFF
OVI
SLOPE
N.C.
RTCT
SGND
SYNC
SS
FB
COMP
CS
REG5
PGND
OUT
V CC
EP
FUNCTION
Input Power Supply. Bypass IN with a minimum 0.1μF ceramic capacitor to PGND.
ON/ OFF Input. Connect ON/ OFF to IN for always-on operation. To externally program the UVLO threshold of the
IN supply, connect a resistive divider between IN, ON/ OFF , and SGND. Pull ON/ OFF to SGND to disable the
controller.
Overvoltage Comparator Input. Connect a resistive divider between the output of the power supply, OVI, and
SGND to set the output overvoltage threshold.
Programmable Slope Compensation Capacitor Input. Connect a capacitor (C SLOPE ) to SGND to set the amount
of slope compensation.
Slope compensation = (2.5 x 10 -9 ) / C SLOPE mV/μs with C SLOPE in farads.
No Connection. Not internally connected.
Oscillator-Timing Network Input. Connect a resistor from RTCT to REG5 and a capacitor from RTCT to SGND to
set the oscillator frequency (see the Oscillator Frequency/External Synchronization section).
Signal Ground. Connect SGND to SGND plane.
External-Clock Synchronization Input. Connect SYNC to SGND when not using an external clock.
Soft-Start Capacitor Input. Connect a capacitor from SS to SGND to set the soft-start time interval.
Internal Error-Amplifier Inverting Input. The noninverting input is internally connected to SS.
Error-Amplifier Output. Connect the frequency compensation network between FB and COMP.
Current-Sense Input. The current-sense signal is compared to a signal proportional to the error-amplifier output
voltage.
5V Low-Dropout Regulator Output. Bypass REG5 with a 1μF ceramic capacitor to SGND.
Power Ground. Connect PGND to the power ground plane.
Gate Driver Output. Connect OUT to the gate of the external n-channel MOSFET.
7.4V Low-Dropout Regulator Output—Driver Power Source. Bypass V CC with 0.1μF and 1μF or higher ceramic
capacitors to PGND.
Exposed Pad (MAX15004A/MAX15005A only). Connect EP to the SGND plane to improve thermal performance.
Do not use the EP as an electrical connection.
Maxim Integrated
9
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