参数资料
型号: MAX15023ETG/V+T
厂商: Maxim Integrated Products
文件页数: 21/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24WQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1MHz
占空比: 87.5%
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
Type III Compensation Network
(See Figure 5)
If the output capacitor used is a low-ESR tantalum or
ceramic type, the ESR-induced zero frequency is usual-
ly above the targeted zero crossover frequency (f O ). In
2) The gain of the modulator (Gain MOD )—composed of
the regulator ’s pulse-width modulator, LC filter,
feedback divider, and associated circuitry at
crossover frequency is:
( 2 π × f O OUT OUT
) × L
× C
this case, Type III compensation is recommended.
Type III compensation provides three poles and two
zeros at the following frequencies:
Gain MOD =
V IN
V OSC
×
2
1
f Z 1 =
f Z 2 =
1
2 π × R F × C F
1
2 π × C I × ( R 1 + R I )
The gain of the error amplifier (Gain EA ) in midband fre-
quencies is:
Gain EA = 2 π × f O × C I × R F
The total loop gain as the product of the modulator gain
Two midband zeros (f Z1 and f Z2 ) cancel the pair of
complex poles introduced by the LC filter:
and the error amplifier gain at f O should be equal to 1.
So:
f P1 = 0
f P1 introduces a pole at zero frequency (integrator) for
nulling DC output voltage errors:
Therefore:
Gain MOD × Gain EA = 1
( 2 π × f O ) × C OUT × L OUT
f P 2 =
1
2 π × R I × C I
V IN
V OSC
×
2
1
× 2 π × f O × C I × R F = 1
f P 3 =
2 π × R F ×
V OSC × ( 2 π × f O × L OUT × C OUT )
V IN × R F
Depending on the location of the ESR zero (f ZO ), f P2
can be used to cancel it, or to provide additional atten-
uation of the high-frequency output ripple:
1
C F × C CF
C F + C CF
f P3 attenuates the high-frequency output ripple.
The locations of the zeros and poles should be such
that the phase margin peaks around f O .
Ensure that R F >>2/g m (1/g m (MIN) = 1/600μS = 1.67k ? )
and the parallel resistance of R 1 , R 2 , and R I is greater
than 1/g m . Otherwise, a 180° phase shift is introduced
to the response and will make it unstable.
The following procedure is recommended:
1) With R F ≥ 10k ? , place the first zero (f Z1 ) at 0.5 x
f PO :
Solving for C I :
C I =
3) If f PO < f O < f ZO < f SW /2, the second pole (f P2 )
should be used to cancel f ZO . This way, the Bode
plot of the loop gain plot does not flatten out soon
after the 0dB crossover, and maintains its
-20dB/decade slope up to 1/2 the switching frequen-
cy. This is likely to occur if the output capacitor is a
low-ESR tantalum or polymer. Then set:
f P2 = f ZO
If a ceramic capacitor is used, then the capacitor ESR
zero, f ZO , is likely to be located even above 1/2 the
switching frequency, that is, f PO < f O < f SW /2 < f ZO . In
this case, the frequency of the second pole (f P2 ) should
be placed high enough in order not to significantly
erode the phase margin at the crossover frequency. For
so:
f Z 1 =
1
2 π × R F × C F
= 0 . 5 × f PO
example, it can be set at 5 x f O , so that its contribution
to phase loss at the crossover frequency, f O , is only
about 11°:
f P2 = 5 x f O
Once f P2 is known, calculate R I :
Maxim Integrated
C F =
1
2 π × R F × 0 . 5 × f PO
R I =
1
2 π × f P 2 × C I
21
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