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参数资料
| 型号： | MAX1510ETB+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/13页 |
| 文件大小： | 0K |
| 描述： | IC CONVERTER DDR 10TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 应用： | 转换器，DDR |
| 输入电压： | 1.1 V ~ 3.6 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 供应商设备封装： | 10-TDFN-EP（3x3） |
| 包装： | 标准包装 |
| 其它名称： | MAX1510ETB+TDKR |
Low-Voltage DDR Linear Regulators
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
—
NAME
REFOUT
V CC
AGND
REFIN
PGOOD
OUTS
SHDN
PGND
OUT
IN
EP
FUNCTION
Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over
5mA. Bypass REFOUT to AGND with a 0.33μF or greater ceramic capacitor.
Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass V CC to AGND with a 1μF or
greater ceramic capacitor.
Analog Ground. Connect the backside pad to AGND.
External Reference Input. REFIN sets the output regulation voltage (V OUTS = V REFIN ).
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above
or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the
regulation voltage during startup, PGOOD becomes high impedance.
Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the
remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12k Ω
resistor.
Shutdown Control Input. Connect to V CC for normal operation. Connect to analog ground to shut down the
linear regulator. The reference buffer remains active in shutdown.
Power Ground. Internally connected to the output sink MOSFET.
Output of the Linear Regulator
Power Input. Internally connected to the output source MOSFET.
Exposed Pad. Internally connected to AGND. Connect EP to AGND PCB ground plane to maximize
thermal performance. Not intended as an electrical connection point.
Detailed Description
The MAX1510/MAX17510 are low-voltage, low-dropout
DDR termination linear regulators with an external bias
supply input and a buffered reference output (see
Figures 1 and 2). V CC is powered by a 2.7V to 3.6V
V IN =
1.1V TO 3.6V
C IN2
10 μ F
IN
OUT
V OUT = V TT = V DDQ /2
C OUT1
100 μ F
supply that is commonly available in laptop and desk-
top computers. The 3.3V bias supply drives the gate of
MAX1510
the internal pass transistor, while a lower voltage input
at the drain of the transistor (IN) is regulated to provide
V OUT . By using separate bias and power inputs, the
MAX1510/MAX17510 can drive an n-channel high-side
3.3V BIAS
SUPPLY
R3
100k Ω
C1
1.0 μ F
V CC
MAX17510
PGND
AGND
MOSFET and use a lower input voltage to provide bet-
POWER-GOOD
ter efficiency.
PGOOD
OUTS
The MAX1510/MAX17510 regulate their output voltage
to the voltage at REFIN. When used in DDR applica-
OFF
ON
SHDN
tions as a termination supply, the MAX1510/MAX17510
deliver 1.25V or 0.9V at 3A peak (typ) from an input
voltage of 1.1V to 3.6V. The MAX1510/MAX17510 sink
up to 3A peak (typ) as required in a termination sup-
ply. The MAX1510/MAX17510 provide shoot-through
V DDQ
R1
10k Ω
R2
10k Ω
C REFIN
1000pF
REFIN
REFOUT
V REFOUT = V TTR
C REFOUT
0.33 μ F
protection, ensuring that the source and sink
MOSFETs do not conduct at the same time, yet pro-
duce a fast source-to-sink load transient.
Figure 1. Standard Application Circuit
_______________________________________________________________________________________
7
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