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参数资料
| 型号： | MAX1536ETI+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3.6A 28TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 5.5 V |
| 输入电压： | 3 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1.4MHz |
| 电流 - 输出： | 3.6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V IN = V CC = V SHDN = +3.3V, V REFIN = +1.5V, SKIP = AGND, T A = 0°C to +85°C , unless otherwise noted. Typical
values are at T A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I CC + I IN
SHDN = AGND; current into V CC and IN;
LX = 0 or +3.3V
0.2
20
Shutdown Supply Currents
I IN
I LX
SHDN = AGND; current into IN; LX = 0
SHDN = AGND; current into LX; LX = +3.3V
0.2
0.1
20
20
μA
REFERENCE
REF Voltage
V REF
V CC = V IN = +3.0V to +5.5V
1.985
2.000
2.015
V
REF Load Regulation
I REF = -1μA to +50μA
10
mV
REFIN Input Voltage Range
REFIN Input Bias Current
V REFIN
I REFIN
V CC = V IN = +3.0V to +5.5V, V CC > V REFIN + 1.35V
V REFIN = 1.5V, V FB = 1.01 × V REFIN
0.7
-50
2.0
+50
V
nA
FAULT DETECTION
Thermal Shutdown
T SHDN
Rising, hysteresis = 15°C
165
°C
Undervoltage Lockout
Threshold
V CC and V IN rising, hysteresis 60mV typical
V CC - V REFIN , V CC rising, hysteresis 60mV typical
2.4
2.6
0.9
2.8
1.35
V
V CC - V FB , V CC rising, hysteresis 60mV typical
0.9
1.35
PGOOD Lower Trip Threshold
PGOOD Upper Trip Threshold
PGOOD Propagation Delay
PGOOD Output Low Voltage
PGOOD Leakage Current
t PGOOD
No load, falling edge, hysteresis = 1% (Note 4)
No load, rising edge, hysteresis = 1% (Note 4)
FB forced 2% beyond PGOOD trip threshold
I SINK = 1mA
High-impedance state, forced to +5.5V
FBLANK = V CC
-12.5
+8.0
112
-10
+10
5
150
-8.0
+12.5
0.1
1
188
%
%
μs
V
μA
Fault Blanking Time
t FBLANK
FBLANK = open or AGND
75
100
125
μs
FBLANK = REF
37
50
63
INPUTS AND OUTPUTS
V SHDN ,
SHDN , SKIP , GATE, V IN = V CC = +3.3V,
rising edge, hysteresis = 100mV
0.9
1.3
1.6
Logic Input Threshold
Logic Input Current
V SKIP ,
V GATE
SHDN , SKIP , GATE, V IN = V CC = +5.0V,
rising edge, hysteresis = 100mV
SHDN , SKIP , GATE
1.15
-0.5
1.55
1.95
+0.5
V
μA
FBLANK = V CC
V CC - 0.2
FBLANK Logic Thresholds
V FBLANK
FBLANK = REF
FBLANK = open
1.8
0.8
2.2
1.2
V
FBLANK = AGND
0.2
FBLANK Input Current
OD On-Resistance
OD Leakage Current
OD On-Resistance
OD Leakage Current
I FBLANK
R OD
R OD
FBLANK forced to AGND or V CC
GATE = V CC
GATE = AGND, V OD = +5.5V
GATE = AGND
GATE = V CC , V OD = +5.5V
-5
-50
-50
10
10
+5
25
+50
25
+50
μA
?
nA
?
nA
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