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参数资料
| 型号： | MAX1536ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3.6A 28TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 5.5 V |
| 输入电压： | 3 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1.4MHz |
| 电流 - 输出： | 3.6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
Pin Description
PIN
1, 21,
24, 26
2, 3,
19, 20
4
5
6
7
8, 25
9
10
11
12
13
14
15
16
NAME
LX
IN
SHDN
SKIP
FB
COMP
N.C.
TOFF
GATE
OD
OD
REFIN
REF
AGND
V CC
FUNCTION
Inductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifier
switch. Connect all LX pins together.
Power Input. Power input for the internal PMOS switch. Connect all IN pins together.
Shutdown Control Input. Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs.
Drive SHDN high or connect to V CC for normal operation.
Pulse-Skipping Control Input. Connect SKIP to V CC for low-noise, forced-PWM mode. Connect SKIP to AGND
for high-efficiency Idle Mode.
Feedback Input. The voltage at REFIN sets the feedback regulation voltage (V FB = V REFIN ).
Integrator Compensation. Connect a 470pF capacitor from COMP to V CC for integrator compensation.
See the Integrator Amplifier section.
No Connection. Not internally connected. Connecting pin 25 to LX eases PC board layout.
Off-Time Select Input. Sets the PMOS power switch off-time during constant off-time operation. Connect a
resistor from TOFF to AGND to adjust the PMOS switch off-time. See the Programming the No-Load Switching
Frequency and Off-Time section.
Buffered OD and OD Control Input. A logic low on GATE forces OD low and OD high impedance. A logic high
on GATE forces OD high impedance and OD low.
Open-Drain Output. A logic low on GATE forces OD high impedance. A logic high on GATE forces OD low.
Inverted Open-Drain Output. A logic low on GATE forces OD low. A logic high on GATE forces OD high
impedance.
External Reference Input. The voltage at REFIN sets the feedback regulation voltage (V FB = V REFIN ).
+2.0V Reference Voltage Output. Bypass REF to AGND with a minimum capacitance of 0.22μF. REF supplies
up to 50μA for external loads. The internal reference turns off in shutdown.
Analog Ground. Connect backside pad to AGND.
Analog Power Input. Power input to the internal analog circuitry. Bypass V CC with a 10 ? and 2.2μF (min)
lowpass filter (Figure 1).
Fault-Blanking Control Input. FBLANK is a four-level logic input that enables or disables fault blanking, and sets
the minimum forced-PWM operation time (t FBLANK ). Enabling fault blanking forces PGOOD high for the selected
time period after a transition is detected on GATE. Additionally, the controller enters forced-PWM mode for the
duration of t FBLANK anytime GATE changes states. Connect FBLANK to the following pins to select t FBLANK and
17
FBLANK fault blanking:
V CC = 150μs (typ), fault blanking enabled
Open = 100μs (typ), fault blanking enabled
REF = 50μs (typ), fault blanking enabled
AGND = 100μs (typ), fault blanking disabled
Open-Drain Power-Good Output. PGOOD is low during soft-start, in shutdown, and when the output voltage is
18
22, 23,
27, 28
PGOOD
PGND
more than 10% (typ) above or below the normal regulation point. After the soft-start, PGOOD becomes high
impedance if the output is in regulation. PGOOD is blanked—forced into a high-impedance state—when
FBLANK is enabled and a transition is detected on GATE.
Power Ground. Internally connected to the source of the internal NMOS synchronous-rectifier switch.
Connect all PGND pins together.
8
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