参数资料
型号: MAX1544ETL+T
厂商: Maxim Integrated Products
文件页数: 22/42页
文件大小: 0K
描述: IC QUICK-PWM DUAL-PHASE 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器,AMD Hammer
输入电压: 2 V ~ 28 V
输出数: 1
输出电压: 0.68 V ~ 1.55 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
SUS
1 LSB PER R TIME CYCLE
V DAC
OUTPUT SET BY SUS AND S0-S1
OUTPUT SET BY D0 – D4
t SLEW
t BLANK = 24 CLKS
t SLEW
t BLANK = 24 CLKS
TIME
CLOCK
VROK
VROK BLANKING
Figure 4. Suspend Transition
as the surge current is less than the current limit set by
ILIM. The transition time is given by:
VROK BLANKING
Fault Protection
Output Overvoltage Protection
f SLEW ? ?
? for V OUT ri sin g
t SLEW ≈
1 ? V OLD ? V NEW ?
V LSB ?
The MAX1544 features selectable output OVP. Connect
OVP to V CC to enable the output overvoltage-fault pro-
tection. The OVP circuit is designed to protect the CPU
1 ? ? V OLD ? V NEW ? ?
f SLEW ? ? ?
? ?
t SLEW ≈ ? ? ? + 2 ? for V OUT falling
V LSB ?
where f SLEW = 500kHz ? 30k ? / R TIME , V OLD is the
original DAC setting, V NEW is the new DAC setting, and
V LSB = 25mV is the DAC ’ s smallest voltage increment.
The additional two clock cycles on the falling edge time
are due to internal synchronization delays. See TIME
Frequency Accuracy in the Electrical Characteristics for
f SLEW limits.
The practical range of R TIME is 15k ? to 150k ? , corre-
sponding to 1.0μs to 10μs per 25mV step. Although the
DAC takes discrete steps, the output filter makes the
transitions relatively smooth. The average inductor cur-
rent required to make an output voltage transition is:
I L ? C OUT × V LSB × f SLEW
against a shorted high-side MOSFET by drawing high
current and blowing the battery fuse. The MAX1544
continuously monitors the output for an overvoltage
fault. During normal forced-PWM operation ( SKIP =
high), the controller detects an OVP fault if the output
voltage exceeds the set DAC voltage by more than 13%
(min). During pulse-skipping operation ( SKIP = REF or
GND), the controller detects an OVP fault if the output
voltage exceeds the fixed 2.0V (typ) threshold. When
the OVP circuit detects an overvoltage fault, it immedi-
ately sets the fault latch and activates the shutdown
sequence.
This action discharges the output filter capacitor and
forces the output to ground. If the condition that caused
the overvoltage (such as a shorted high-side MOSFET)
persists, the battery fuse blows. The controller remains
shut down until the fault latch is cleared by toggling
SHDN or cycling the V CC power supply below 1V.
To disable the overvoltage protection, connect OVP to
GND. The OVP is also disabled when the controller is in
the no-fault test mode (see the No-Fault Test Mode
section).
22
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