参数资料
型号: MAX1587CETL+
厂商: Maxim Integrated Products
文件页数: 15/30页
文件大小: 0K
描述: IC POWER MANAGEMENT 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
应用: 手持/移动设备
电源电压: 2.6 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 管件
High-Efficiency, Low-I Q PMICs with
Dynamic Core for PDAs and Smart Phones
Pin Description (continued)
PIN
MAX
1586
16
17
18
19
20
21
22
23
MAX
1587
13
14
15
16
17
18
19
20
NAME
PV2
LX2
PG2
IN
RAMP
GND
REF
BYP
FUNCTION
REG2 Power Input. Bypass to PG2 with a 4.7μF or greater low-ESR capacitor. PV1, PV2, PV3, and IN must
connect together externally.
REG2 Switching Node. Connects to REG2 inductor.
REG2 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.
Main Battery Input. This input provides power to the IC.
V3 Ramp-Rate Control. A capacitor connected from RAMP to GND sets the rate-of-change when V3 is
changed. The output impedance of RAMP is 100k Ω . FB3 regulates to 1.28 x V RAMP .
Analog Ground
Reference Output. Output of the 1.25V reference. Bypass to GND with a 0.1μF or greater capacitor.
Low-Noise LDO Bypass. Low-noise bypass pin for V4 LDO. Connect a 0.01μF capacitor from BYP to GND.
Dead or Missing Battery Output. DBO is an open-drain output that goes low when V IN is below the
24
DBO
threshold set by DBI. DBO does not deactivate any MAX1586/MAX1587 regulator outputs. DBO is
expected to connect to nBATT_FAULT on Intel CPUs.
On/Off Input for REG2. Drive high to turn on. When enabled, the REG2 output soft-starts. ON2 has
25
21
ON2
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 are connected to SYS_EN.
On/Off Input for REG4. Drive high to turn on. When enabled, the REG4 output activates. ON4 has hysteresis
26
ON4
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that
ON4 is connected to PWR_EN.
27
28
29
23
24
25
V4
IN45
V5
Also Known as VCC_PLL. 1.3V, 35mA linear-regulator output for PLL. Regulator input is IN45.
Power Input to V4 and V5 LDOs. Typically connected to V2, but can also connect to IN or another voltage
from 2.5V to V IN .
Also Known as VCC_SRAM. 1.1V, 35mA linear-regulator output for CPU SRAM. Regulator input is IN45.
On/Off Input for REG5. Drive high to turn on. When enabled, the MAX1586/MAX1587 soft-starts the REG5
30
ON5
output. ON5 has hysteresis so an RC can be used to implement manual sequencing with respect to other
inputs. It is expected that ON5 is connected to PWR_EN.
31
32
33
26
27
28
PG3
LX3
PV3
REG3 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.
REG3 Switching Node. Connects to the REG3 inductor.
REG3 Power Input. Bypass to PG3 with a 4.7μF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and
IN must connect together externally.
On/Off Input for REG3 (Core). Drive high to turn on. When enabled, the REG3 output ramps up. ON3 has
34
34
ON3
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON3 is driven from CPU SYS_EN.
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