参数资料
型号: MAX16034PLB29+T
厂商: Maxim Integrated Products
文件页数: 10/21页
文件大小: 0K
描述: IC BATTERY BACKUP 2.93V 10-UDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.93V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN
供应商设备封装: 10-uDFN(2x2)
包装: 带卷 (TR)
Low-Power Battery Backup
Circuits in Small μDFN Packages
Backup Battery Switchover
To preserve the contents of the RAM in a brownout or
power failure, the MAX16033–MAX16040 automatically
switch to back up the battery installed at BATT when
the following two conditions are met:
1) V CC falls below the reset threshold voltage.
2) V CC is below V BATT .
Table 1 lists the status of the inputs and outputs in bat-
tery-backup mode. The devices do not power-up if the
only voltage source is V BATT . OUT only powers up from
V CC at startup.
Table 1. Input and Output Status in
Battery-Backup Mode
V CC . This input can be driven from TTL/CMOS logic
outputs or with open-drain/collector outputs. Connect a
normally-open momentary switch from MR to GND to
create a manual-reset function; external debounce cir-
cuitry is not required. When driving MR from long
cables or when using the device in a noisy environ-
ment, connect a 0.1μF capacitor from MR to GND to
provide additional noise immunity.
Watchdog Input
(MAX16034/MAX16038 Only)
The watchdog monitors μP activity through the watch-
dog input (WDI). RESET asserts when the μP fails to
toggle WDI. Connect WDI to a bus line or μP I/O line. A
change of state (high to low, low to high, or a minimum
100ns pulse) resets the watchdog timer. If WDI remains
high or low for longer than the watchdog timeout period
PIN
V CC
OUT
BATT
RESET
BATTON
MR , RESETIN,
CE IN, and WDI
CE OUT
STATUS
Disconnected from OUT
Connected to BATT
Connected to OUT. Current drawn from the
battery is less than 1μA (at V BATT = 2.8V,
excluding I OUT ) when V CC = 0V.
Asserted
High state
Inputs ignored
Connected to OUT
(t WD ), the internal watchdog timer runs out and triggers
a reset pulse for the reset timeout period (t RP ). The
internal watchdog timer clears whenever reset is
asserted or whenever WDI sees a rising or falling edge.
If WDI remains in either a high or low state, a reset
pulse periodically asserts after every watchdog timeout
period (t WD ); see Figure 2.
WDI
PFO
Asserted
Manual-Reset Input
(MAX16033/MAX16037 Only)
t WD
RESET
t WD = WATCHDOG TIMEOUT PERIOD
t RP = RESET TIMEOUT PERIOD
t RP
t WD
t RP
Many μP-based products require manual-reset capabil-
ity, allowing the user or external logic circuitry to initiate
a reset. For the MAX16033/MAX16037, a logic-low on
MR asserts RESET . RESET remains asserted while MR
is low and for a minimum of 140ms (t RP ) after it returns
high. MR has an internal 20k ? (min) pullup resistor to
Figure 2. MAX16034/MAX16038 Watchdog Timeout Period and
Reset Active Time
10
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