参数资料
型号: MAX16037PLA23+T
厂商: Maxim Integrated Products
文件页数: 9/21页
文件大小: 0K
描述: IC BATTERY BACKUP 2.32V 8-UDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 备用电池电路
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.32V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN
供应商设备封装: 8-uDFN(2x2)
包装: 带卷 (TR)
Low-Power Battery Backup
Circuits in Small μDFN Packages
Detailed Description
The Typical Operating Circuit shows a typical connec-
tion for the MAX16033–MAX16040. OUT powers the
static random-access memory (SRAM). If V CC is
greater than the reset threshold (V TH ), or if V CC is lower
than V TH but higher than V BATT , V CC is connected to
OUT. If V CC is lower than V TH and V CC is less than
V BATT , BATT is connected to OUT. OUT supplies up to
200mA from V CC . In battery-backup mode, an internal
MOSFET connects the backup battery to OUT. The on-
resistance of the MOSFET is a function of the backup-
battery voltage and temperature and is shown in the
BATT-to-OUT On-Resistance vs. Temperature graph in
the Typical Operating Characteristics.
Chip-Enable Signal Gating
(MAX16033–MAX16036 Only)
The MAX16033–MAX16036 provide internal gating of
chip-enable ( CE ) signals to prevent erroneous data
from being written to CMOS RAM in the event of a
power failure or brownout condition. During normal
operation, the CE gate is enabled and passes all CE
transitions. When reset asserts, this path becomes
disabled, preventing erroneous data from corrupting
the CMOS RAM. The MAX16033–MAX16036 provide a
series transmission gate from CE IN to CE OUT. A 2ns
(typ) propagation delay from CE IN to CE OUT allows
V CC
V TH
CEIN
CEOUT
RESET-TO-CEOUT DELAY
t RD
these devices to be used with most μPs and high-
speed DSPs.
When RESET is deasserted, CE IN is connected to
CE OUT through a low on-resistance transmission gate.
If CE IN is high when RESET is asserted, CE OUT
remains high regardless of any subsequent transitions
on CE IN during the reset event.
If CE IN is low when RESET is asserted, CE OUT is held
low for 1μs to allow completion of the read/write opera-
tion (Figure 1). After the 1μs delay expires, CE OUT
goes high and stays high regardless of any subsequent
transitions on CE IN during the reset event. When
CE OUT is disconnected from CE IN, CE OUT is actively
pulled up to OUT.
The propagation delay through the chip-enable circuit-
ry depends on both the source impedance of the drive
to CE IN and the capacitive loading at CE OUT. The
chip-enable propagation delay is specified from the
50% point of CE IN to the 50% point of CE OUT, using a
50 ? driver and 50pF load capacitance. Minimize the
capacitive load at CE OUT and use a low output-imped-
ance driver to minimize propagation delay.
In high-impedance mode, the leakage current at CE IN
is ±1μA (max) over temperature. In low-impedance
mode, the impedance of CE IN appears as a 75 ? resis-
tor in series with the load at CE OUT.
*
t RD
RESET
PFO
PFI > V PFI
t RP
t RP
* IF CEIN GOES HIGH BEFORE RESET ASSERTS,
CEOUT GOES HIGH WITHOUT DELAY AS CEIN GOES HIGH.
Figure 1. RESET and Chip-Enable Timing
_______________________________________________________________________________________
9
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