参数资料
型号: MAX16042TP+
厂商: Maxim Integrated Products
文件页数: 3/15页
文件大小: 0K
描述: IC SUPERVISOR CIRC TRPL 20TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 75
类型: 序列发生器
监视电压数目: 3
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 140 ms/可调最小值
电压 - 阀值: 9 种可选阀值组合
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 管件
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.2V to 28V, T A = -40 ° C to +125 ° C, unless otherwise specified. Typical values are at V CC = 3.3V and T A = +25 ° C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CRESET AND CDLY_
CRESET Threshold
CRESET Charge Current
CDLY_ Threshold
CDLY_ Charge Current
V TH-RESET
I CH-RESET
V TH-CDLY
I CH-CDLY
CRESET rising, V CC = 3.3V
V CC = 3.3V
CDLY_ rising, V CC = 3.3V
V CC = 3.3V
0.465
380
0.95
200
0.5
500
1
250
0.535
620
1.05
300
V
nA
V
nA
DIGITAL LOGIC INPUTS (EN_, M R , TOL, TH1, TH0)
Input Low Voltage
Input High Voltage
TH1, TH0 Logic-Input Floating
V IL
V IH
1.4
0.6
0.4
V
V
V
TOL, TH1, TH0 Logic-Input
Current
EN_ Input Leakage Current
V TOL , V TH1 , V TH0 = GND or V CC
V EN_ = V CC or GND
-1
-100
+1
+100
μA
nA
MR Internal Pullup Current
V CC = 3.3V
250
535
820
nA
OUTPUTS (OUT_, RESET )
Output Low Voltage
(Open-Drain or Push-Pull)
Output High Voltage (Push-Pull)
Output Leakage Current
(Open-Drain)
V OL
V OH
I LKG
V CC ≥ 1.2V, I SINK = 90μA
V CC ≥ 2.25V, I SINK = 0.5mA
V CC ≥ 4.5V, I SINK = 1mA
V CC ≥ 3V, I SOURCE = 500μA
V CC ≥ 4.5V, I SOURCE = 800μA
Output not asserted low, V OUT = 28V
0.8 x V CC
0.8 x V CC
0.3
0.3
0.35
1
V
V
μA
Reset Timeout Period
t RP
CRESET = V CC , V CC = 3.3V
CRESET open
140
190
0.030
260
ms
TIMING
IN_ to OUT_ Propagation Delay
t DELAY+
t DELAY-
IN_ rising, CDLY_ open
IN_ falling, CDLY_ open
35
20
μs
IN_ to RESET Propagation Delay
MR Minimum Input Pulse Width
EN_ or MR Glitch Rejection
t RST-DELAY CRESET open, IN_ falling
(Note 3)
t OFF
From device enabled to device disabled
2
35
280
3
μs
μs
ns
EN_ to OUT_ Delay
MR to RESET Delay
t ON
From device disabled to device enabled
(CDLY_ open)
MR falling
30
3
μs
μs
Note 1: Devices are production tested at T A = +25°C. Limits over temperature are guaranteed by design.
Note 2: Operating below the UVLO causes all outputs to go low. The outputs are guaranteed to be in the correct state for V CC down
to 1.2V.
Note 3: To guarantee an assertion, the minimum input pulse width must be greater than 2μs.
_______________________________________________________________________________________
3
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