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参数资料
| 型号： | MAX1604 |
| 厂商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual-Channel CardBus and PCMCIA Power Switches with SMBus⑩ Serial Interface |
| 中文描述： | 双通道CardBus和PCMCIA电源开关，带有SMBus串行接口 |
| 文件页数： | 12/16页 |
| 文件大小： | 190K |
| 代理商： | MAX1604 |
M
Dual-Channel CardBus and PCMCIA
Power S witc hes with S MBus S erial Interfac e
12
______________________________________________________________________________________
______S MBus Interfac e Operation
The SMBus serial interface is a two-wire interface with
multi-mastering capability, intended to control low-
speed peripheral devices in low-power portable equip-
ment applications. SMBus is similar to I
2
C and
AccessBus, but has slightly different logic threshold
voltage levels, different fixed addresses, and a sus-
pend-mode register capability. To obtain a complete
set of specifications on the SMBus interface, call Intel at
(800) 253-3696 and ask for product code SBS5220.
S MBus Addressing
These dual-channel PC Card switch devices respond to
two of four different addresses, depending on the state
of the ADR address pin. Normal writing to the device is
done by transmitting one of four addresses, followed by
a single data byte, to program the channel selected.
Write transmissions to the interrupt pointer address are
not supported by these devices. Reading from the
device is done by transmitting one of two addresses cor-
responding to either the A channel address (which will
provide data about faults for both A and B channels) or
to the interrupt pointer address (discussed later).
The normal start condition consists of a high-to-low
transition on SMBDATA while SMBCLK is high. The
7-bit address is followed by a bit that designates a read
or write operation: high = read, low = write. If the 7-bit
address matches one of the supported function
addresses, the IC issues an acknowledge pulse by
pulling the SMBDATA line low. If the address is not
valid, the IC stays off of the bus and ignores any data
on the bus until a new start condition is detected. Once
the IC receives a valid address that includes a write bit,
it expects to receive one additional byte of data. If a
stop condition or new start condition is detected before
a complete byte of data is clocked in, the IC interprets
this as an error and all of the data is rejected and lost.
SMBDATA and SMBCLK are Schmitt triggered and can
accommodate slower edges. However, rising edges
should still be faster than 1
μ
s, and falling edges should
be faster than 300ns.
S MBus Write Operations
If the IC receives a valid address immediately followed
by a write bit, the IC becomes a slave receiver. The
slave IC generates a first acknowledge after the
address and write bit, and a second acknowledge after
the command byte. A stop condition following the com-
mand (data) byte causes immediate execution of the
command, unless the data included a low SUS/OP bit.
If the data included a low SUS/OP bit, the command is
stored in the suspend-mode register and is executed
only when the SMBSUS pin is pulled low (Figure 3).
Table 1. SMBus Addressing
SMB
ADDRESS
ADR PIN
WRITE
FUNCTION
READ FUNCTION
0001100
1010000
1010001
1010010
1010011
Don’t care
Grounded
Grounded
Tied to VL
Tied to VL
N/A
Interrupt Pointer
Channel A/B faults
Channel A/B faults
Channel A/B faults
Channel A/B faults
Channel A
Channel B
Channel A
Channel B
Table 2. Command Format for Channel A Write Operations (address 1010000 or 1010010)
I
2
C is a trademark of Philips Corp.
SMBus is a trademark of Intel Corp.
Masks fault interrupts from both channel A and channel B when high.
0
MASKFLT
0 (LSB)
Puts VPPA in a high-impedance state when high. Overrides VPPAON.
0
VPPAHIZ
1
If VPPA is on, a high connects VPPA to 12INA, and a low connects VPPA to VCCA.
0
VPPAPGM
2
Turns on VPPA when high, pulls VPPA to GND when low.
0
VPPAON
3
Puts VCCA in a high-impedance state when high. Overrides VCCAON.
0
VCCAHIZ
4
If VCCA is on, a high connects VY to VCCA, and a low connects VX to VCCA.
0
VCCA3/5
5
Turns on VCCA when high, pulls VCCA to GND when low.
0
VCCAON
6
Operate/suspend bit. Selects which latch receives data: high = operation,
low = suspend.
0
OP/SUS
7 (MSB)
FUNCTION
POR STATE
NAME
BIT
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