参数资料
型号: MAX16070ETL+T
厂商: Maxim Integrated Products
文件页数: 28/52页
文件大小: 0K
描述: IC SYSTEM MANAGER 12CH 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源监控器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 4.5mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 17. Watchdog Configuration
REGISTER
ADDRESS
73h
FLASH
ADDRESS
273h
BIT RANGE
[4]
[7]
DESCRIPTION
1 = Independent mode
0 = Dependent mode
1 = Watchdog affects RESET output
0 = Watchdog does not affect RESET output
Watchdog startup delay
000 = No initial timeout
001 = 30s
010 = 40s
[6:4]
011 = 80s
100 = 120s
101 = 160s
110 = 220s
111 = 300s
Watchdog timeout
0000 = Watchdog disabled
76h
276h
[3:0]
0001 = 1ms
0010 = 2ms
0011 = 4ms
0100 = 8ms
0101 = 14ms
0110 = 27ms
0111 = 50ms
1000 = 100ms
1001 = 200ms
1010 = 400ms
1011 = 750ms
1100 = 1.4s
1101 = 2.7s
1110 = 5s
1111 = 10s
The normal watchdog timeout period, t WDI , begins after
the first transition on WDI before the conclusion of the
long startup watchdog period, t WDI_STARTUP (Figure 5).
During the normal operating mode, WDO asserts if the
F P does not toggle WDI with a valid transition (high-to-
low or low-to-high) within the standard timeout period,
t WDI . WDO remains asserted until WDI is toggled or
RESET is asserted (Figure 6).
While EN is low, the watchdog timer is in reset. The
watchdog timer does not begin counting until RESET is
deasserted. The watchdog timer is reset and WDO deas-
serts any time RESET is asserted (Figure 7). The watch-
dog timer will be held in reset while RESET is asserted.
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET asserts for
the reset timeout, t RP , when the watchdog timer expires
and the Watchdog Reset Output Enable bit (r76h[7]) is
set to ‘1.’ When RESET is asserted, the watchdog timer
is cleared and WDO is deasserted, therefore, WDO
pulses low for a short time (approximately 1 F s) when
the watchdog timer expires. RESET is not affected by
the watchdog timer when the Watchdog Reset Output
Enable bit (r76h[7]) is set to ‘0.’ If a RESET is asserted
by the watchdog timeout, the WDRESET bit is set to ‘1’. A
connected processor can check this bit to see the reset
was due to a watchdog timeout. See Table 17 for more
information on configuring watchdog functionality.
28
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