参数资料
型号: MAX1644EAE-T
厂商: Maxim Integrated Products
文件页数: 10/11页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 16SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.1 V ~ 5.5 V
输入电压: 3 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 最高 350kHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.209",5.30mm 宽)
包装: 带卷 (TR)
供应商设备封装: 16-SSOP
2A Low-Voltage, Step-Down Regulator with
Synchronous Rectification and Internal Switches
Soft-Start
Soft-start allows a gradual increase of the internal cur-
rent limit to reduce input surge currents at start-up and
at exit from shutdown. A charging capacitor, C SS ,
SHDN
placed from SS to GND sets the rate at which the inter-
nal current limit is changed. Upon power-up, when the
device comes out of undervoltage lockout (2.6V typ) or
after the SHDN pin is pulled high, a 5μA constant-cur-
rent source charges the soft-start capacitor and the
V SS (V)
0
0
0.7V
1.8V
voltage on SS increases. When the voltage on SS is
less than approximately 0.7V, the current limit is set to
zero. As the voltage increases from 0.7V to approxi-
mately 1.8V, the current limit is adjusted from 0 to 2.9A.
The voltage across the soft-start capacitor changes
with time according to the equation:
I LIMIT (A)
0
2.9A
t
V SS =
5 μ A × t
C SS
Figure 3. Soft-Start Current Limit over Time
The soft-start current limit varies with the voltage on the
soft-start pin, SS, according to the equation:
I LIMIT = (V SS - 0.7V) · 2.7A/V, for V SS > 0.7V
The constant-current source stops charging once the
voltage across the soft-start capacitor reaches 1.8V
(Figure 3).
Circuit Layout and Grounding
Good layout is necessary to achieve the MAX1644’s
intended output power level, high efficiency, and low
noise. Good layout includes the use of a ground plane,
appropriate component placement, and correct routing
of traces using appropriate trace widths. The following
points are in order of decreasing importance:
1) Minimize switched-current and high-current ground
loops. Connect the input capacitor’s ground, the out-
put capacitor’s ground, and PGND together.
2) Connect the input filter capacitor less than 5mm
away from IN. The connecting copper trace carries
large currents and must be at least 2mm wide,
preferably 5mm.
3) Place the LX node components as close together
and as near to the device as possible. This reduces
resistive and switching losses as well as noise.
4) A ground plane is essential for optimum perfor-
mance. In most applications, the circuit is located on
a multilayer board, and full use of the four or more
layers is recommended. Use the top and bottom lay-
ers for interconnections and the inner layers for an
uninterrupted ground plane.
___________________Chip Information
TRANSISTOR COUNT: 1758
10
______________________________________________________________________________________
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