参数资料
型号: MAX1655ESE+
厂商: Maxim Integrated Products
文件页数: 3/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 350kHz
占空比: 98%
电源电压: 4.5 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 1410 (CN2011-ZH PDF)
High-Efficiency, PWM, Step-Down
DC-DC Controllers in 16-Pin QSOP
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +15V, GND = PGND = 0V, SYNC = REF, I VL = I REF = 0A, T A = 0°C to +85°C, unless otherwise noted.)
PARAMETER
Reference Output Voltage
CONDITIONS
No external load (Note 1)
MIN
2.46
TYP
2.50
MAX
2.54
UNITS
V
Reference Fault Lockout Voltage
Reference Load Regulation
CSL, CSH Shutdown Leakage
Current
V+ Shutdown Current
V+ Off-State Leakage Current
Dropout Power Consumption
Quiescent Power Consumption
Falling edge
0 < I REF < 100μA
SHDN = 0V, CSL = 5.5V, CSH = 5.5V, V+ = 0 or 30V,
VL = 0V
SHDN = 0V, V+ = 30V, CSL = 0 or 5.5V
FB = CSH = CSL = 5.5V, VL switched over to CSL
V+ = 4.5V, CSH = CSL = 4.0V (Note 2)
CSH = CSL = 5.5V
2.0
5
0.1
3
5
1
1
2.4
15
1
7
15
8
2
V
mV
μA
μA
μA
mW
mW
OSCILLATOR AND INPUTS/OUTPUTS
Oscillator Frequency
SYNC = REF
SYNC = 0 or 5V
270
125
300
150
330
175
kHz
SYNC High Pulse Width
SYNC Low Pulse Width
200
200
ns
ns
SYNC Rise/Fall Time
Oscillator Sync Range
Guaranteed by design, not tested
190
200
340
ns
kHz
Dropout-Mode Maximum Duty
Cycle
SYNC = REF
SYNC = 0 or 5V
97
98
98
99
%
Input High Voltage
Input Low Voltage
Input Current
DL Sink/Source Current
DH Sink/Source Current
SYNC
SHDN, SKIP
SYNC
SHDN, SKIP
SHDN, 0 or 30V
SECFB, 0 or 4V
SYNC, SKIP
CSH, CSL, CSH = CSL ≤ 4V
FB, FB = REF
DL forced to 2V
DH forced to 2V, BST - LX = 4.5V
VL - 0.5
2.0
1
1
0.8
0.5
3.0
0.1
1.0
70
±0.1
V
V
μA
A
A
DL On-Resistance
DH On-Resistance
High or low
High or low, BST - LX = 4.5V
1.5
1.5
5
5
?
?
Note 1: Since the reference uses VL as its supply, V+ line-regulation error is insignificant.
Note 2: At very low input voltages, quiescent supply current may increase due to excessive PNP base current in the VL linear
regulator. This occurs if V+ falls below the preset VL regulation point (5V nominal).
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