参数资料
型号: MAX1668MEE+
厂商: Maxim Integrated
文件页数: 4/17页
文件大小: 497K
描述: IC TEMP SENSOR MULTI-CHAN 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
功能: 温度计,恒温计
传感器类型: 内部和外部
感应温度: -55°C ~ 125°C,外部传感器
精确度: ±3.5°C 本地(最大),±5°C 远程(最大)
拓扑: ADC,比较器,多路复用器,寄存器库
输出类型: I²C?/SMBus?
输出警报:
输出风扇:
电源电压: 3 V ~ 5.5 V
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 管件
产品目录页面: 1425 (CN2011-ZH PDF)
0
8
4
16
12
20
24
FREQUENCY (MHz)
TEMPERATURE ERROR
vs. SUPPLY NOISE FREQUENCY
100mV
P-P
0.1
1
10
100
WITH V
CC
 0.1礔 CAPACITOR REMOVED
2200pF BETWEEN DXN_ AND DXP_
250mV
P-P
20
-20
1
10
100
TEMPERATURE ERROR
vs. PC BOARD RESISTANCE
-10
LEAKA E RE I TAN E M&
0
10
PATH = DXP_ TO GND
PATH = DXP_ TO V
CC
(5V)
-2
-1
0
1
2
3
4
-50
-10
-30
10   30   50   70   90  110
TEMPERATURE ERROR
vs. TEMPERATURE
TEMPERAT RE ?/DIV>
NPN (CMPT3904)
PNP (CMPT3906)
INTERNAL
Typical Operating Characteristics
(Typical Operating Circuit, V
CC
= +5V, STBY = V
CC
, configuration byte = X0XXXX00, T
A
= +25癈, unless otherwise noted.)
Multichannel Remote/Local
Temperature Sensors
4  _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +5V, STBY = V
CC
, configuration byte = X0XXXX00, T
A
= -55癈 to +125癈, unless otherwise noted.) (Note 6)
Note 1:  Guaranteed by design, but not production tested.
Note 2:  Quantization error is not included in specifications for temperature accuracy. For example, if the MAX1668/MAX1805/
MAX1989 device temperature is exactly +66.7癈, the ADC may report +66癈, +67癈, or +68癈 (due to the quantization
error plus the +0.5癈 offset used for rounding up) and still be within the guaranteed ?癈 error limits for the +60癈 to
+100癈 temperature range. See Table 2.
Note 3:  A remote diode is any diode-connected transistor from Table 1. T
R
is the junction temperature of the remote diode. See the
Remote-Diode Selection section for remote-diode forward-voltage requirements.
Note 4:  The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it
violates the 10kHz minimum clock frequency and SMBus specifications, and can monopolize the bus.
Note 5:  Note that a transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of
SMBCLKs falling edge t
HD:DAT.
Note 6:  Specifications from -55?/SPAN>C to +125?/SPAN>C are guaranteed by design, not production tested.
CONDITIONS
UNITS
MIN
TYP
MAX
PARAMETER
STBY, SMBCLK, SMBDATA; V
CC
= 4.5V to 5.5V
Logic Input High Voltage
V
2.4
ALERT forced to 5.5V
1
ALERT Output High Leakage
Current
Logic inputs forced to V
CC
or GND
-2
+2
Logic Input Current
ALERT, SMBDATA forced to 0.4V
mA
6
Logic Output Low Sink Current
STBY, SMBCLK, SMBDATA; V
CC
= 4.5V to 5.5V
V
0.8
Logic Input Low Voltage
SMBus INTERFACE
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