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| 型号： | MAX1677EEE-T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BST SYNC 0.35A DL 16QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 升压（升压） |
| 输出类型： | 两者兼有 |
| 输出数： | 2 |
| 输出电压： | 3.3V 或可调主电源，-28 V ~ 28 V 或可调副电源 |
| 输入电压： | 0.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 300kHz |
| 电流 - 输出： | 350mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-QSOP |
Compact, High-Efficiency, Dual-Output
Step-Up and LCD Bias DC-DC Converter
During PFM operation, the error comparator detects
when the output voltage is out of regulation and sets a
flip-flop, turning on the N-channel MOSFET switch
(Figure 5). When the inductor current ramps to the PFM
mode current limit (350mA), the current-sense compara-
tor resets a flip-flop. The flip-flop turns off the N-channel
switch and turns on the P-channel synchronous rectifier.
The energy stored in the inductor is transferred to the
output through the P-channel switch. A second flip-flop,
previously reset by the switch ’ s “ on ” signal, inhibits the
next cycle until the inductor current is depleted and the
output is out of regulation. This forces operation with
discontinuous inductor current in PFM mode.
Startup Oscillator
The MBC employs a low-voltage startup oscillator to
ensure a 1.1V (0.9V typical) startup voltage. On start-
up, if the output voltage is less than 2.25V, the P-chan-
nel switch stays off and the N-channel pulses at a 25%
duty cycle. When the output voltage exceeds 2.25V,
the normal PWM or PFM control circuitry takes over.
Once the MBC is in regulation, it can operate with
inputs down to 0.7V since the internal power for the IC
Table 2. Selecting MBC Operating Mode
is taken from OUT. The MBC cannot supply full output
current until OUT reaches 2.5V.
Synchronous Rectifier
The MAX1677 MBC features an internal 1 ? P-channel
synchronous rectifier. Synchronous rectification typical-
ly improves efficiency by 5% or more over similar non-
synchronous step-up designs. In PWM mode, the
synchronous rectifier turns on during the second half of
each cycle. In PFM mode, an internal comparator turns
on the synchronous rectifier when the voltage at LX
exceeds the MBC output, and then turns it off when the
inductor current drops below 90mA (typ).
The on-chip synchronous rectifier allows the external
Schottky diode to be omitted in designs that operate
from inputs exceeding 1.4V. In circuits operating below
1.4V (1-cell inputs, for example), connecting a Schottky
diode in parallel with the internal synchronous rectifier
(from LX to POUT) provides the lowest startup voltage.
LCD Boost Converter (LCD)
The LCD converter can be configured for a positive or
negative output by setting the LCDPOL pin and using
the appropriate circuit (Figures 2 and 3, and Table 3).
A combination of peak current limiting and a pair of
one-shot timers control LCD switching. During the on-
CLK/SEL
0
1
Ext Clock
(200Hz to
400kHz)
MBC MODE
Low-Power PFM
PWM
Synchronized
PWM
FEATURES
Lowest Supply Current
High Output Current,
Fixed-Frequency Ripple
High Output Current,
Synchronized Ripple
Frequency
cycle the internal N-channel DMOS switch turns on,
and inductor current ramps up until either the switch
peak current limit is reached or the 5.2μs maximum on-
time expires (typically at low input voltages). After the
on-cycle terminates, the switch turns off and the output
capacitor charges. The switch remains off until the error
comparator initiates another cycle.
The LCDLX current limit is set by LCDPOL, as outlined
in Table 3. The lower, 225mA peak current setting
allows tiny low-current “ chip ” inductors to be used
Q
Q
R
D
LOGIC HIGH
POUT
when powering smaller (less than 15 square inches)
liquid crystal panels. Use the following equation to
determine which LCDLX current-limit setting is
required.
P
LX
I LCD = (0.7 × I PK(LCD) × V IN(MIN) ) / (2 × V LCD(MAX) )
where I LCD is the output current, V IN(MIN) is the mini-
mum expected input voltage, V LCD(MAX) is the maxi-
V FB
V REF
CURRENT
LIMIT LEVEL
S
R
Q
N
PGND
mum required LCD output voltage, and I PK(LCD) is
350mA or 225mA as set by LCDPOL. The 0.7 term is a
correction factor to conservatively account for typical
switch, inductor, and diode losses.
The LCD boost is enabled when both ON and LCDON
are high, and the MBC output voltage is within 90% of
its set value. A soft-start startup mode with increased
Figure 5. Controller Block Diagram in PFM Mode
______________________________________________________________________________________
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