参数资料
型号: MAX16806ATP+T
厂商: Maxim Integrated
文件页数: 5/19页
文件大小: 0K
描述: IC LED DRIVR HIGH BRIGHT 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
恒定电流:
拓扑: PWM
输出数: 1
内部驱动器:
类型 - 主要: 车载
类型 - 次要: 高亮度 LED(HBLED)
频率: 400kHz
电源电压: 5.5 V ~ 40 V
输出电压: 5.1V
安装类型: 表面贴装
封装/外壳: 20-WQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(5x5)
包装: 带卷 (TR)
工作温度: -40°C ~ 125°C
EEPROM-Programmable, High-Voltage, 350mA
LED Drivers with LED Current Foldback
ELECTRICAL CHARACTERISTICS (continued)
(V IN = V EN = 12V, C V5 = 0.1μF, I V5 = 0, CS- = GND, R SENSE = 0.56 Ω , V DIM = 4V, DGND = GND, TFP/SCL = 5V, TFN/SDA = 0V,
SW = CFD = Open, T A = T J = -40°C to +125°C, unless otherwise noted. Typical values are at T A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM
V IN Voltage for EEPROM
Programming
EEPROM Data-Retention Time
20
10
22
24
V
Years
I 2 C DIGITAL INPUTS (TFP/SCL, TFN/SDA) (Note 5)
Logic Input-Voltage High
Logic Input-Voltage Low
Input Capacitance
V IH
V IL
2.8
5
0.8
V
V
pF
SDA Output Voltage Low
V OL
I SINK = 3mA
0.4
V
I 2 C INTERFACE TIMING (Figure 1)
Serial Clock Frequency
Bus Free Time Between STOP
and START Condition
START Condition Hold Time
Clock Low Period
Clock High Period
Repeat START Condition Setup
Time
f SCL
t BUF
t HD:STA
t LOW
t HIGH
t SU:STA
1.3
0.6
1.3
0.6
0.6
400
kHz
μs
μs
μs
μs
μs
A master device must provide a hold time
of at least 300ns for the SDA signal
Data Hold Time
t HD:DAT
(referred to V IL of the SCL signal) in order
0
0.9
μs
to bridge the undefined region of SCL’s
falling edge
Data Setup Time
Receive SCL/SDA Rise Time
Receive SCL/SDA Fall Time
STOP Condition Setup Time
Pulse Width of Spike Suppressed
Transmit SDA Fall Time
t SU:DAT
t R
t F
t SU:STO
t SP
I SINK < 6mA, C B ≤ 400pF (Note 6)
100
0.6
50
300
250
250
ns
ns
ns
μs
ns
ns
Note 1: All devices 100% production tested at T J = +25°C. Limits over the operating temperature range are guaranteed by design.
Note 2: Resistors were added from OUT to CS+ to aid with the power dissipation during testing.
Note 3: Dropout is measured as follows: Connect a resistor from OUT to CS+. Connect R SENSE = 0.56 Ω from CS+ to CS-. Set V IN =
V OUT +3V (record V OUT as V OUT1 ). Reduce V IN until V OUT = 0.97 x V OUT1 (record as V IN2 and V OUT2 ). Δ V DO = V IN2 - V OUT2 .
Note 4: t ON time includes the delay and the rise time needed for I OUT to reach 90% of its final value. t OFF time is the time needed for
I OUT to drop below 10%. See the Typical Operating Characteristics. t ON and t OFF are tested with 13 Ω from OUT to CS+.
Note 5: TPF/SCL (SCL for MAX16805) and TPN/SDA (SDA for the MAX16805) are I 2 C interface compatible only when the
MAX16805/MAX16806 are the only parts on the bus for production programming.
Note 6: C B is the total bus capacitance.
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