参数资料
型号: MAX16825EVKIT+
厂商: Maxim Integrated Products
文件页数: 12/13页
文件大小: 0K
描述: KIT EVAL FOR MAX16825
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
电流 - 输出 / 通道: 100mA
输出及类型: 3,非隔离
输出电压: 26.3V
特点: 图形用户界面
输入电压: 6.5 ~ 28 V
已供物品: 板,CD
已用 IC / 零件: MAX16825
MAX16824/MAX16825
High-Voltage, Three-Channel Linear
High-Brightness LED Drivers
A third method is to hold both LE and OE in the
enabled state. This allows the data bits to directly con-
trol the output channels, and hence, pulse dim the out-
put current. Make sure that the clock frequency does
not exceed the maximum rate at which the device can
change the state of the output channels.
Power Dissipation
The power dissipation (P D ) of the MAX16824/
MAX16825 is determined from the following equation:
P D = ( V IN × I IN ) + ( V INL ? V LED 1 ? V CS 1 ) × ( I LED 1 × DUT Y 1 )
+ ( V INL ? V LED 2 ? V CS 2 ) × ( I LED 2 × DUTY 2 )
+ ( V INL ? V LED 3 ? V CS 3 ) × ( I LED 3 × DUTY 3 )
where:
V IN = supply voltage
V INL = supply voltage to the LED strings
V LED_ = total forward voltage for one LED string
I LED_ = LED current
V CS_ = 200mV drop across R CS_
DUTY_ = PWM_ duty cycle
The worst-case power dissipation occurs when the
drop across each internal MOSFET is at its maximum
with all three channels delivering the maximum allow-
able output current. The maximum drop across the
internal MOSFETs is determined by:
V INL - V LED_ - V CS_ when V LED_ is at its minimum.
Higher ambient temperature increases the thermal stress
even further due to the reduction in voltage drop across
the LEDs. The MAX16824/MAX16825 thermal specifica-
tions are given according to the JEDEC-51 guidelines.
Good mechanical/thermal design practices must be
applied to help maintain the device junction temperature
below the absolute maximum ratings at all times.
I IN = supply current
Pin Configurations
TOP VIEW
TOP VIEW
OUT1 1
CS1 2
IN 3
REG 4
N.C. 5
N.C. 6
PWM1 7
PWM2 8
+
MAX16824
16 OUT2
15 CS2
14 N.C.
13 CS3
12 OUT3
11 GND
10 N.C.
9 PWM3
OUT1 1
CS1 2
IN 3
REG 4
N.C. 5
CLK 6
DIN 7
LE 8
+
MAX16825
16 OUT2
15 CS2
14 N.C.
13 CS3
12 OUT3
11 GND
10 DOUT
9 OE
TSSOP-EP
Chip Information
PROCESS: BiCMOS-DMOS
TSSOP-EP
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages . Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
12
PACKAGE
TYPE
16 TSSOP-EP
PACKAGE
CODE
U16E+3
OUTLINE NO.
LAND
PATTERN NO.
Maxim Integrated
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