参数资料
型号: MAX16904SAUE33/V+
厂商: Maxim Integrated Products
文件页数: 10/15页
文件大小: 0K
描述: IC REG BUCK SYNC 3.3V 16TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 3.3V
输入电压: 3.5 V ~ 28 V
PWM 型: 电流模式
频率 - 开关: 2.1MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
MAX16904
2.1MHz, High-Voltage,
600mA Mini-Buck Converter
If the input voltage is reduced and the device
approaches dropout, it tries to turn on the high-side
FET continuously. To maintain gate charge on the high-
side FET, the BST capacitor must be periodically
recharged. To ensure proper charge on the BST
capacitor when in dropout, the high-side FET is turned
off every 6.5μs and the low-side FET is turned on for
about 150ns. This gives an effective duty cycle
of > 97% and a switching frequency of 150kHz when in
dropout.
Spread-Spectrum Option
Applications Information
Inductor Selection
The nominal inductor value can be calculated using
Table based on the nominal output voltage of the
device. Select the nearest standard inductance value to
the calculated nominal value. The nominal standard
value selected should be within ±25% of L NOM for best
performance.
Table 1. Inductor Selection
The device has an optional spread-spectrum version. If
this option is selected, then the internal operating fre-
quency varies by +6% relative to the internally generat-
ed operating frequency of 2.1MHz (typ). Spread
spectrum is offered to improve EMI performance of the
device. By varying the frequency 6% only in the posi-
tive direction, the device still guarantees that the
V OUT (V)
1.8 to 3.1
3.2 to 6.5
6.6 to 8.1
8.2 to 10
L NOM (μH)
V OUT /0.55
V OUT /0.96
V OUT /1.40
V OUT /1.75
2.1MHz frequency does not drop into the AM band limit
of 1.8MHz. Additionally, with the low minimum on-time
of 80ns (typ) no pulse skipping is observed for a 5V
Table 2. Examples for Standard Output
Voltages
output with 18V input maximum battery voltage in
steady state.
The internal spread spectrum does not interfere with
the external clock applied on the SYNC pin. It is active
only when the device is running with internally generat-
ed switching frequency.
Power-Good (PGOOD)
V OUT
(V)
1.8
3.3
5.0
8.0
CALCULATED
L NOM (μH)
3.3
3.4
5.2
5.7
STANDARD
VALUE (μH)
3.3
3.3
4.7
5.6
The device features an open-drain power-good output.
PGOOD is an active-high output that pulls low when the
output voltage is below 91% of its nominal value. PGOOD
is high impedance when the output voltage is above 93%
of its nominal value. Connect a 20k Ω (typ) pullup resistor to
an external supply or the on-chip BIAS output.
Overcurrent Protection
The device limits the peak output current to 1.05A (typ).
To protect against short-circuit events, the device shuts
off when OUTS is below 1.5V (typ) and one overcurrent
event is detected. The device attempts a soft-start
restart every 30ms and stays off if the short circuit has
not been removed. When the current limit is no longer
present, it reaches the output voltage by following the
normal soft-start sequence. If the device die reaches
the thermal limit of +175°C (typ) during the current-limit
event, it immediately shuts off.
Thermal-Overload Protection
The device features thermal-overload protection. The
device turns off when the junction temperature exceeds
+175°C (typ). Once the device cools by 15°C (typ), it
turns back on with a soft-start sequence.
10
Input Capacitor
A low-ESR ceramic input capacitor of 1μF or larger is
needed for proper device operation. This value may
need to be larger based on application input ripple
requirements.
The discontinuous input current of the buck converter
causes large input ripple current. The switching frequen-
cy, peak inductor current, and the allowable peak-to-
peak input-voltage ripple dictate the input capacitance
requirement. Increasing the switching frequency or the
inductor value lowers the peak-to-average current ratio
yielding a lower input capacitance requirement.
The input ripple comprises mainly of Δ V Q (caused by
the capacitor discharge) and Δ V ESR (caused by the
ESR of the input capacitor). The total voltage ripple is
the sum of Δ V Q and Δ V ESR . Assume the input-voltage
ripple from the ESR and the capacitor discharge is
equal to 50% each. The following equations show the
ESR and capacitor requirement for a target voltage rip-
ple at the input:
Maxim Integrated
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