参数资料
型号: MAX16920BATJ/V+
厂商: Maxim Integrated Products
文件页数: 15/20页
文件大小: 0K
描述: IC PMIC MULT-OUTPUT AUTO 32TQFN
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 43
应用: 车载系统
电流 - 电源: 2mA
电源电压: 5.5 V ~ 18 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
供应商设备封装: 56-TQFN-EP(7x7)
包装: 托盘
Automotive Power-Management IC with
Three Step-Down Converters and Linear Regulator
D = OUT
and:
V
V IN
where I OUT is the output current, D is the duty cycle,
and f SW is the switching frequency. Use additional input
capacitance at lower input voltages to avoid possible
undershoot below the UVLO threshold during transient
loading.
Output Capacitor Selection
The allowable output voltage ripple and the maximum
deviation of the output voltage during step load currents
determine the output capacitance and its ESR. The
output ripple is composed of ΔV Q (caused by the
capacitor discharge) and ΔV ESR (caused by the ESR
of the output capacitor). Use low-ESR ceramic or alumi-
num electrolytic capacitors at the output. For aluminum
electrolytic capacitors, the entire output ripple is
contributed by ΔV ESR . Use the ESR OUT equation to cal-
culate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume
the contribution to the output ripple voltage from the
ESR and the capacitor discharge to be equal. The
following equations show the output capacitance and
ESR requirement for a specified output voltage ripple.
ESR = ΔV ESR /ΔI P-P
C OUT = ΔI P-P /(8 x ΔV Q x f SW )
where:
ΔI P-P = (V IN - V OUT ) x V OUT /(V IN x f SW x L)
V OUT_RIPPLE ~ ΔV ESR + ΔV Q
ΔI P-P is the peak-to-peak inductor current as calculated
above, and f SW is the converter’s switching frequency.
The allowable deviation of the output voltage during fast
transient loads also determines the output capacitance
and its ESR. The output capacitor supplies the load-
step current until the converter responds with a greater
Use low-ESR ceramic capacitors for better transient
load and ripple/noise performance. Keep the maximum
output voltage deviations below the tolerable limits of
the electronics being powered. When using a ceramic
capacitor, assume an 80% and 20% contribution from
the output capacitance discharge and the ESR drop,
respectively. Use the following equations to calculate the
required ESR and capacitance value:
ESR OUT = ΔV ESR /I STEP
C OUT = (I STEP x t RESPONSE )/ΔV Q
where I STEP is the load step, and t RESPONSE is the
response time of the converter. The converter response
time depends on the control-loop bandwidth.
Electrolytic output capacitors can be used if a 2.2μF
ceramic capacitor is connected in parallel. At output
currents lower than the maximum, smaller capacitors
can be used. Use a 4.7μF or larger ceramic capacitor
on the output of the linear regulator, OUTA.
Setting the Output Voltage (DC-DC1,
DC-DC2, DC-DC3)
The output voltage for any of the DC-DC converters is
set by selecting resistor R1 according to the formula:
R1 = R2 x ((V OUT_ /1.22) - 1)
where V OUT_ is the desired output voltage, and R2 is the
value of the ground connected resistor (a good starting
value is 30k?). See Figure 2. When setting DC-DC1 or
DC-DC3 to output voltages higher than 3.3V , it is neces-
sary to add an additional resistive divider between the
converter output and the OUT1 or OUT3 pins. Resistor
values of 100k? and 50k? work well in all applications.
See Figure 3 for the exact configuration.
OUT_
R1
duty cycle. The response time (t RESPONSE ) depends on
the closed-loop bandwidth of the converter. The high
switching frequency of the MAX16920 allows for a higher
closed-loop bandwidth, thus reducing t RESPONSE and
the output capacitance requirement. The resistive drop
MAX16920
FB_
GND
R2
across the output capacitor’s ESR and the capacitor
discharge causes a voltage droop during a load step.
Figure 2. Setting the Output Voltage
15
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