参数资料
型号: MAX17003AETJ+
厂商: Maxim Integrated Products
文件页数: 5/36页
文件大小: 0K
描述: IC PS CTLR FOR NOTEBOOKS 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
应用: 控制器,笔记本电脑电源系统
输入电压: 6 V ~ 26 V
输出数: 4
输出电压: 3.3V,5V,2 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 管件
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V IN = 12V, both SMPS enabled, FSEL = REF, SKIP = GND, ILIM = LDO5, FBA = LDO5, I REF = I LDO5 = I OUTA =
no load, T A = 0°C to +85°C , unless otherwise noted. Typical values are at T A = +25°C.)
PARAMETER
PGDALL Lower Trip Threshold
PGDALL Propagation Delay
SYMBOL
t PGDALL
CONDITIONS
With respect to either SMPS error-comparator
threshold, hysteresis = 1% (typ)
Falling edge, 50mV overdrive
Rising edge, 50mV overdrive
MIN
-12
TYP
-10
10
1
MAX
-8
UNITS
%
μs
PGDALL Output Low Voltage
I SINK = 1mA
0.4
V
PGDALL Leakage Current
Thermal-Shutdown Threshold
I PGDALL
t SHDN
High state, PGDALL forced to 5.5V
Hysteresis = 15°C
+160
1
μA
°C
GATE DRIVERS
DH_ Gate-Driver On-Resistance
DL_ Gate-Driver On-Resistance
DH_ Gate-Driver
Source/Sink Current
DL_ Gate-Driver Source Current
DL_ Gate-Driver Sink Current
R DH
R DL
I DH
I DL
I DL (SINK)
BST_ - LX_ forced to 5V
DL_, high state
DL_, low state
DH_ forced to 2.5V, BST_ - LX_
forced to 5V
DL_ forced to 2.5V
DL_ forced to 2.5V
1.3
1.7
0.6
2
1.7
3.3
5
5
3
Ω
Ω
A
A
A
Dead Time
Internal BST_ Switch
On-Resistance
BST_ Leakage Current
t DEAD
R BST
DH_ low to DL_ high
DL_ low to DH_ high
I BST = 10mA
V BST _ = 26V
15
15
45
44
5
2
20
ns
Ω
μA
INPUTS AND OUTPUTS
SHDN Input Trip Level
Rising trip level
Falling trip level
1.1
0.96
1.6
1
2.2
1.04
V
ONA Logic Input Voltage
Hysteresis = 600mV
(typ)
High
Low
2.4
0.8
V
SMPS off level/clear fault level
0.8
ON3, ON5 Input Voltage
Delay start level
1.9
2.1
V
SMPS on level
2.4
DSCHG_ Output Low Voltage
DSCHG_ Leakage Current
I SINK = 1mA
High state, DSCHG_ forced to 5.5V
0.4
1
V
μA
Tri-Level Input Logic
SKIP , FSEL
High
REF
V LDO5
- 0.4
1.65
2.35
V
GND
0.5
Input Leakage Current
SKIP , FSEL forced to GND or LDO5
SHDN forced to GND or 26V
-1
-1
+1
+1
μA
_______________________________________________________________________________________
5
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