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参数资料
| 型号： | MAX17048G+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | IC FUEL/GAS GAUGE LI-ION 8TDFN |
| 标准包装： | 1 |
| 系列： | ModelGauge™ |
| 功能： | 燃料，电量检测计/监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 2.5 V ~ 4.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN-EP（2x2） |
| 包装： | 管件 |
MAX17048/MAX17049
Micropower 1-Cell/2-Cell Li+ ModelGauge ICs
I 2 C Bus System
The I 2 C bus system supports operation as a slave-only
device in a single or multislave, and single or multimaster
system. Slave devices can share the bus by uniquely
setting the 7-bit slave address. The I 2 C interface con-
sists of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL provide bidirectional communica-
tion between the IC’s slave device and a master device
at speeds up to 400kHz. The IC’s SDA pin operates
bidirectionally; that is, when the IC receives data, SDA
operates as an input, and when the IC returns data, SDA
operates as an open-drain output, with the host system
providing a resistive pullup. The IC always operates as
a slave device, receiving and transmitting data under
the control of a master device. The master initiates all
transactions on the bus and generates the SCL signal, as
well as the START and STOP bits, which begin and end
each transaction.
Bit Transfer
One data bit is transferred during each SCL clock cycle,
with the cycle defined by SCL transitioning low-to-high
and then high-to-low. The SDA logic level must remain
stable during the high period of the SCL clock pulse.
Any change in SDA when SCL is high is interpreted as a
START or STOP control signal.
Bus Idle
The bus is defined to be idle, or not busy, when no
master device has control. Both SDA and SCL remain
high when the bus is idle. The STOP condition is the
proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition
(S) by forcing a high-to-low transition on SDA while SCL
Acknowledge Bits
Each byte of a data transfer is acknowledged with an
acknowledge bit (A) or a no-acknowledge bit (N). Both
the master and the MAX17048 slave generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep
it low until SCL returns low. To generate a no- acknowl-
edge (also called NAK), the receiver releases SDA before
the rising edge of the acknowledge-related clock pulse
and leaves SDA high until SCL returns low. Monitoring
the acknowledge bits allows for detection of unsuccess-
ful data transfers. An unsuccessful data transfer can
occur if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master should reattempt communication.
Data Order
A byte of data consists of 8 bits ordered most significant
bit (MSb) first. The least significant bit (LSb) of each
byte is followed by the acknowledge bit. The IC registers
composed of multibyte values are ordered MSB first.
The MSB of multibyte registers is stored on even data-
memory addresses.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address (SAddr) and the read/write (R/W) bit.
When the bus is idle, the ICs continuously monitor for
a START condition followed by its slave address. When
the ICs receive a slave address that matches the value
in the slave address register, they respond with an
acknowledge bit during the clock period following the
R/W bit. The 7-bit slave address is fixed to 0x6C
(write)/0x6D (read):
is high. The master terminates a transaction with a STOP
condition (P), a low-to-high transition on SDA while SCL
is high. A Repeated START condition (Sr) can be used
MAX17048 /MAX17049
SLAVE ADDRESS
0110110
in place of a STOP then START sequence to terminate
one transaction and begin another without returning the
bus to the idle state. In multimaster systems, a Repeated
START allows the master to retain control of the bus. The
START and STOP conditions are the only bus activities in
which the SDA transitions when SCL is high.
Maxim Integrated
Read/Write Bit
The R/W bit following the slave address determines
the data direction of subsequent bytes in the transfer.
R/W = 0 selects a write transaction with the following
bytes being written by the master to the slave. R/W = 1
selects a read transaction with the following bytes being
read from the slave by the master ( Table 4 ).
16
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX17048G+ | 功能描述:电池管理 Host-Side Modelgauge (1-Cell) RoHS:否 制造商:Texas Instruments 电池类型:Li-Ion 输出电压:5 V 输出电流:4.5 A 工作电源电压:3.9 V to 17 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:VQFN-24 封装:Reel |
| MAX17048G+T10 | 功能描述:电池管理 Host-Side Modelgauge (1-Cell) RoHS:否 制造商:Texas Instruments 电池类型:Li-Ion 输出电压:5 V 输出电流:4.5 A 工作电源电压:3.9 V to 17 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:VQFN-24 封装:Reel |
| MAX17048X+ | 功能描述:电池管理 Host-Side Modelgauge (1-Cell) RoHS:否 制造商:Texas Instruments 电池类型:Li-Ion 输出电压:5 V 输出电流:4.5 A 工作电源电压:3.9 V to 17 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:VQFN-24 封装:Reel |
| MAX17048X+T10 | 功能描述:电池管理 Host-Side Modelgauge (1-Cell) RoHS:否 制造商:Texas Instruments 电池类型:Li-Ion 输出电压:5 V 输出电流:4.5 A 工作电源电压:3.9 V to 17 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:VQFN-24 封装:Reel |
| MAX17049EVKIT# | 功能描述:电源管理IC开发工具 MAX17049 Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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