参数资料
型号: MAX17049G+
厂商: Maxim Integrated Products
文件页数: 17/19页
文件大小: 0K
描述: IC FUEL/GAS GAUGE LI-ION 8TDFN
标准包装: 1
系列: ModelGauge™
功能: 燃料,电量检测计/监控器
电池化学: 锂离子(Li-Ion)
电源电压: 2.5 V ~ 4.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
供应商设备封装: 8-TDFN-EP(2x2)
包装: 管件
MAX17048/MAX17049
Micropower 1-Cell/2-Cell Li+ ModelGauge ICs
Table 4. I 2 C Protocol Key
KEY
S
SAddr
MAddr
Data
A
N
DESCRIPTION
START bit
Slave address (7 bit)
Memory address byte
Data byte written by master
Acknowledge bit—master
No acknowledge—master
KEY
Sr
W
P
Data
A
N
R
DESCRIPTION
Repeated START
R/W bit = 0
STOP bit
Data byte returned by slave
Acknowledge bit—slave
No acknowledge bit—slave
R/W bit = 1
Bus Timing
The ICs are compatible with any bus timing up to
400kHz. No special configuration is required to operate
at any speed.
I 2 C Command Protocols
The command protocols involve several transaction
formats. The simplest format consists of the master
The master indicates the end of a read transaction by
responding to the last byte it requires with a no acknowl-
edge. This signals the ICs that control of SDA is to remain
with the master following the acknowledge clock.
Write: S. SAddr W. A . MAddr. A . Data0. A . Data1. A . P
Read: S. SAddr W. A . MAddr. A . Sr. SAddr R. A . Data0 . A. Data1 . N. P
writing the START bit, slave address, R/W bit, and then
Write Portion
Read Portion
monitoring the acknowledge bit for presence of the ICs.
More complex formats, such as the Write Data and Read
Data, read data and execute device-specific operations.
All bytes in each command format require the slave or
host to return an acknowledge bit before continuing with
the next byte. Table 4 shows the key that applies to the
transaction formats.
Basic Transaction Formats
A write transaction transfers 2 or more data bytes to the
ICs. The data transfer begins at the memory address
supplied in the MAddr byte. Control of the SDA signal is
retained by the master throughout the transaction, except
for the acknowledge cycles:
A read transaction transfers 2 or more bytes from the
ICs. Read transactions are composed of two parts,
a write portion followed by a read portion, and are
therefore inherently longer than a write transaction. The
write portion communicates the starting point for the
read operation. The read portion follows immediately,
beginning with a Repeated START, slave address with
R/W set to a 1. Control of SDA is assumed by the ICs,
beginning with the slave address acknowledge cycle.
Control of the SDA signal is retained by the ICs through-
out the transaction, except for the acknowledge cycles.
Maxim Integrated
Write Data Protocol
The write data protocol is used to write to register to the
ICs starting at memory address MAddr. Data0 represents
the data written to MAddr, Data1 represents the data
written to MAddr + 1, and DataN represents the last data
byte, written to MAddr + N. The master indicates the end
of a write transaction by sending a STOP or Repeated
START after receiving the last acknowledge bit:
S. SAddr W. A . MAddr. A. Data0. A. Data1. A... DataN. A. P
The MSb of the data to be stored at address MAddr can
be written immediately after the MAddr byte is acknowl-
edged. Because the address is automatically increment-
ed after the LSb of each byte is received by the ICs, the
MSb of the data at address MAddr + 1 can be written
immediately after the acknowledgment of the data at
address MAddr. If the bus master continues an autoin-
cremented write transaction beyond address 4Fh, the
ICs ignore the data. A valid write must include both reg-
ister bytes. Data is also ignored on writes to read-only
addresses. Incomplete bytes and bytes that are not
acknowledged by the ICs are not written to memory.
17
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