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参数资料
| 型号： | MAX17500BEUB+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/18页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST ISO PWM 10-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 625kHz |
| 占空比： | 75% |
| 电源电压： | 36 V ~ 72 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 带卷 (TR) |
Current-Mode PWM Controllers with
Programmable Switching Frequency
point, the internal regulator begins charging C2 (see
Figure 1). Only 50μA of the current supplied through R1
is used by the MAX17500; the remaining input current
MAX17499/MAX17500 fig02
V CC
2V/div
V IN
5V/div
0V
100ms/div
Figure 2. V IN and V CC During Startup When Using the
MAX17500 in Bootstrapped Mode (Figure 1)
For the MAX17500, the voltage at IN is normally derived
from a tertiary winding of the transformer. However, at
startup there is no energy being delivered through the
transformer; hence, a special bootstrap sequence is
required. Figure 2 shows the voltages at V IN and V CC
during startup. Initially, both V IN and V CC are 0V. After
the line voltage is applied, C1 charges through the
startup resistor, R1, to an intermediate voltage. At this
1.23V
( ± 1%)
V UVLO/EN
HIGH-Z
charges C1 and C2. The charging of C2 stops when
the V CC voltage reaches approximately 9.5V, while the
voltage across C1 continues rising until it reaches the
wake-up level of 21.6V. Once V IN exceeds the boot-
strap UVLO threshold, NDRV begins switching the
MOSFET and transfers energy to the secondary and
tertiary outputs. If the voltage on the tertiary output
builds to higher than 9.74V (the bootstrap UVLO lower
threshold), then startup has been accomplished and
sustained operation commences. If V IN drops below
9.74V before startup is complete, the device goes back
to low-current UVLO. In this case, increase the value of
C1 to store enough energy to allow for the voltage at
the tertiary winding to build up.
UVLO Flag (UFLG)
The devices have an open-drain undervoltage flag out-
put (UFLG). When used with an optocoupler, the UFLG
output can serve to sequence a secondary-side con-
troller. An internal 210μs delay occurs the instant the
voltage on UVLO/EN drops below 1.17V until NDRV
stops switching. This allows for the UFLG output to
change state before the devices shut down (Figure 3).
When the voltage at the UVLO/EN is above the thresh-
old, UFLG is high impedance. When UVLO/EN is below
the threshold, UFLG goes low. UFLG is not affected by
bootstrap UVLO (MAX17500).
1.17V (typ)
V UFLG
V NDRV
LOW
SHUTDOWN
3 μ s
0.6 μ s
NDRV SWITCHING
LOW
SHUTDOWN
Figure 3. UVLO/EN and UFLG Operation Timing
t EXTR
3ms
t EXTF
210 μ s
10
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| MAX17501AATB+T | 功能描述:电流型 PWM 控制器 65V.5A 600kHz Synch Step-Down RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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| MAX17501AEUB+T | 功能描述:电流型 PWM 控制器 65V.5A 600kHz Synch Step-Down RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| MAX17501ATEVKIT# | 功能描述:电源管理IC开发工具 MAX17501A Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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