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参数资料
| 型号： | MAX17605AUA+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR 4A DUAL 8UMAX |
| 标准包装： | 50 |
| 配置： | 低端 |
| 输入类型： | 反相和非反相 |
| 延迟时间： | 12ns |
| 电流 - 峰： | 4A |
| 配置数： | 2 |
| 输出数： | 2 |
| 电源电压： | 4 V ~ 14 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
MAX17600–MAX17605
4A Sink /Source Current, 12ns, Dual MOSFET Drivers
Undervoltage Lockout (UVLO)
When V DD is below the UVLO threshold, the output
stage n-channel device is on and the p-channel is off,
independent of the state of the inputs. This holds the
outputs low. The UVLO is typically 3.6V with 200mV
typical hysteresis to avoid chattering. A typical falling
delay of 2 F s makes the UVLO immune to narrow negative
transients in noisy environments.
Driver Outputs
The devices feature 4A peak sourcing/sinking capa-
bilities to provide fast rise and fall times of the MOSFET
gate. Add a resistor in series with OUT_ to slow the cor-
responding rise/fall time of the MOSFET gate.
Applications Information
Supply Bypassing, Device
Grounding, and Placement
Ample supply bypassing and device grounding are
extremely important because when large external
capacitive loads are driven, the peak current at the V DD
pin can approach 4A, while at the GND pin, the peak
current can approach 4A. V DD drops and ground shifts
are forms of negative feedback for inverters and, if
excessive, can cause multiple switching when the
inverting input is used and the input slew rate is low. The
device driving the input should be referenced to the devic-
es’ GND pin, especially when the inverting input is used.
Ground shifts due to insufficient device grounding can
disturb other circuits sharing the same AC ground return
path. Any series inductance in the V DD , OUT_, and/or
GND paths can cause oscillations due to the very high
di/dt that results when the devices are switched with any
capacitive load. A 2.2 F F or larger value ceramic
capacitor is recommended, bypassing V DD to GND and
placed as close as possible to the pins. When driving
very large loads (e.g., 10nF) at minimum rise time, 10 F F or
more of parallel storage capacitance is recommended. A
ground plane is highly recommended to minimize ground
return resistance and series inductance. Care should be
taken to place the devices as close as possible to the
external MOSFET being driven to further minimize board
inductance and AC path resistance.
Power Dissipation
Power dissipation of the devices consists of three
components, caused by the quiescent current, capacitive
charge and discharge of internal nodes, and the output
current (either capacitive or resistive load). The sum of
these components must be kept below the maximum
power-dissipation limit.
The quiescent current is 1mA typical. The current
required to charge and discharge the internal nodes
is frequency dependent (see the Typical Operating
Characteristics ). The devices’ power dissipation when
driving a ground referenced resistive load is:
P = D x R ON (MAX) x I LOAD 2 per channel
where D is the fraction of the period the devices’ output
pulls high, R ON (MAX) is the maximum pullup on-resist-
ance of the device with the output high, and I LOAD is the
output load current of the devices.
For capacitive loads, the power dissipation is:
P = C LOAD x (V DD ) 2 x FREQ per channel
where C LOAD is the capacitive load, V DD is the supply
voltage, and FREQ is the switching frequency.
Layout Information
The devices’ MOSFET drivers source and sink large
currents to create very fast rise and fall edges at the
gate of the switching MOSFET. The high di/dt can cause
unacceptable ringing if the trace lengths and
impedances are not well controlled. The following PCB
layout guidelines are recommended when designing with
the devices:
? Place at least one 2.2 F F decoupling ceramic capacitor
from V DD to GND as close as possible to the IC. At least
one storage capacitor of 10 F F (min) should be located
on the PCB with a low-resistance path to the V DD pin
of the devices. There are two AC current loops formed
between the IC and the gate of the MOSFET being
driven. The MOSFET looks like a large capacitance
from gate to source when the gate is being pulled low.
The active current loop is from OUT_ of the devices to
the MOSFET gate to the MOSFET source and to GND
of the devices. When the gate of the MOSFET is being
pulled high, the active current loop is from OUT_ of the
devices to the MOSFET gate to the MOSFET source to
the GND terminal of the decoupling capacitor to the
V DD terminal of the decoupling capacitor and to the
V DD terminal of the devices. While the charging current
loop is important, the discharging current loop is also
critical. It is important to minimize the physical distance
and the impedance in these AC current paths.
? In a multilayer PCB, the component surface layer
surrounding the devices should consist of a ground plane
containing the discharging and charging current loops.
10
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相关代理商/技术参数 |
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| MAX17605AUA+ | 功能描述:功率驱动器IC 4A Sink/Source 12ns Dual MOSFET Driver RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| MAX17605AUA+T | 功能描述:功率驱动器IC Dual MOSFET Driver RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| MAX17605EVKIT# | 功能描述:电源管理IC开发工具 MAX17605 Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| MAX1760ETB | 制造商:Maxim Integrated Products 功能描述:0.8A, LOW-NOISE, 1MHZ, STEP-UP DC-DC CONVERTE - Rail/Tube |
| MAX1760ETB+ | 制造商:Maxim Integrated Products 功能描述:CONV DC-DC SGL-OUT STEP UP 10TDFN EP - Rail/Tube |
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