参数资料
型号: MAX1761EEE+
厂商: Maxim Integrated Products
文件页数: 8/23页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
PWM 型: 电流模式
输出数: 2
频率 - 最大: 428kHz
电源电压: 4.5 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 管件
Small, Dual, High-Efficiency
Buck Controller for Notebooks
Pin Description
PIN
1
2
3
NAME
FB1
OUT1
REF
FUNCTION
Feedback Input for the 2.5V PWM. Connect FB1 to GND for a fixed 2.5V output. Connect a resistive
voltage-divider to FB1 to adjust OUT1 from 1V to 5.5V. FB1 regulates to 1V (see Adjusting V OUT section) .
Output Voltage Connection for PWM1. OUT1 senses the output voltage to set the regulator on-time
and is connected internally to a 160k ? feedback input in fixed-output mode.
2V Reference Voltage Output. Bypass REF to GND with 0.1 μ F (min) capacitor. Can supply 50 μ A for
external loads.
When ON1 = High, Normal/Forced PWM Mode Selection and OUT2 On/ Off Control Input
ON2 CONDITION
MODE SELECTED
4
ON2
LOW (ON2 < 0.5V)
HIGH (2V < ON2 < VL)
Floating
OUT1 is enabled in normal mode; OUT2 is shut down.
Both outputs are enabled in normal mode.
Both outputs are enabled in forced-PWM mode.
5
6
7
8
9
10
11
12
13
14
15
16
V+
ON1
OUT2
FB2
DH2
CS2
DL2
GND
VL
DL1
CS1
DH1
Battery Voltage. V+ is the input for the VL regulator and DH gate drivers and is also used for PWM
one-shot timing.
On/ Off Control Input. Drive ON1 high to enable the device. Drive ON1 low to enter micropower
shutdown mode. Both REF and VL are disabled in shutdown. ON1 may be pinstrapped to V+.
Output Voltage Connection for PWM2. OUT2 senses the output voltage to set the regulator on-time
and is connected internally to a 160k ? feedback input in fixed-output mode.
Feedback Input for the 1.8V PWM. Connect FB2 to GND for a fixed 1.8V output. Connect a resistive
voltage-divider to FB2 to adjust OUT2 from 1V to 5.5V. FB2 regulates to 1V (see Adjusting V OUT section) .
High-Side Gate Driver Output for PWM2. Swings between GND and V+.
Current-Sense Connection for PWM2. Connect CS2 to the drain of the low-side driver. Alternatively,
connect CS2 to the junction of the source of the low-side FET and a current-sense resistor to GND.
Low-Side Gate Driver Output for PWM2. DL2 swings between GND and VL.
Combined Power and Analog Ground
Linear Regulator Output. VL is the output of the 4.65V internal linear regulator, capable of supplying
25mA for external loads. The VL pin also serves as the supply input for the DL gate driver and the
analog/logic blocks. VL can be overdriven by an external 5V supply to improve efficiency. Bypass
VL to GND with a 4.7 μ F ceramic capacitor.
Low-Side Gate Driver Output for PWM1. DL1 swings between GND and VL.
Current-Sense Connection for PWM1. Connect CS1 to the drain of the low-side driver. Alternatively,
connect CS1 to the junction of the source of the low-side FET and a current-sense resistor to GND.
High-Side Gate Driver Output for PWM1. DH1 swings between GND and V+.
8
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MAX1762EUB 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK