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参数资料
| 型号： | MAX1841EUB+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/8页 |
| 文件大小： | 0K |
| 描述： | IC TRANS LEVEL SIM 10-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 智能卡 |
| 接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 电源电压： | 1.4 V ~ 5.5 V，1.7 V ~ 5.5 V |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-µMAX |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
MAX1840/MAX1841
Low-Voltage SIM/Smart Card
Level Translators in MAX
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(Figure 1, DVCC = +1.8V; VCC = +1.8V, +3.0V, or +5.0V; SHDN = DVCC, CIN = RIN = GND or DVCC, IO = VCC, DATA = DDRV = DVCC,
CIO = CCLK = CRST = CDATA = 30pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note1)
UNITS
CONDITIONS
MIN
TYP
MAX
SYMBOL
PARAMETER
Output Low Level
VOL(DATA)
IO = GND, ISINK = 100A
0.4
V
DVCC = 3.0V, IO = GND, ISINK = 200A
0.4
Output High Level
ISOURCE = 10A
0.7
DVCC
V
DVCC = 3.0V, ISOURCE = 20A
0.7
DVCC
VOH(DATA)
IO Pullup Resistance
RIO
Between IO and VCC
6.5
10
14
k
Input Low Threshold
VIL(IO)
IIL(MAX) = 1mA (Note 2)
0.3
V
Input High Threshold
VIH(IO)
IIH(MAX) = ±20A (Note 3)
0.7
VCC
V
Input Low Current
IIL
1
mA
Input High Current
IIH
20
A
Output Low Level
VOL(IO)
DATA = GND or DDRV = GND,
ISINK = 200A
0.4
V
Output High Level
VOH(IO)
ISOURCE = 20A
0.8
VCC
V
Shutdown Output Levels
(IO, CLK, RST)
ISINK = 200A, SHDN = GND, DATA = CIN =
RIN = DVCC (MAX1840 only)
0.4
V
ISINK = 200A, DVCC = GND, SHDN
(MAX1840) = DDRV (MAX1841) = DATA =
CIN = RIN = DVCC
0.4
V
ISINK = 200A, VCC = GND, SHDN
(MAX1840) = DDRV (MAX1841) = DATA =
CIN = RIN = DVCC
0.4
V
Maximum CLK Frequency
(Notes 4, 5)
fCLK
VCC = 2.7V to 5.5V, DVCC = 1.4V to 2.7V
520
MHz
VCC = 1.7V to 3.6V, DVCC = 1.4V to 2.25V
515
IO (INPUT/OUTPUT)
SHUTDOWN OUTPUT LEVELS
TIMING
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
Note 2: VIL is defined as the voltage at which the output (DATA/IO) voltage equals 0.5V.
Note 3: VIH is defined as the voltage at which the output (DATA/IO) voltage exceeds the input (IO/DATA) voltage by 100mV.
Note 4: Timing specifications are guaranteed by design, not production tested.
Note 5: The maximum CLK frequency is defined as the output duty cycle remaining in the 40% to 60% range when the 50% CIN is
applied. CIN has 5ns rise and fall times; levels are GND to DVCC. Input and output levels are measured at 50% of the waveform.
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