参数资料
型号: MAX1856EUB+T
厂商: Maxim Integrated Products
文件页数: 9/18页
文件大小: 0K
描述: IC PWR SPLY PWM SLIC 10-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,卫星接收机顶盒,xDSL 和线缆调制解调器
输入电压: 3 V ~ 28 V
输出数: 1
输出电压: -24V,-72V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-uMAX
包装: 带卷 (TR)
Wide Input Range, Synchronizable,
PWM SLIC Power Supply
*INPUT
4.5V TO 24V
R5
10 ?
C IN
(2x) 10 μ F
25V
T1
D2
OUT2
-72V
C4
1 μ F
C LDO
1 μ F
9
10
1
2
V CC
SYNC/SHDN
MAX1856
LDO
FREQ
EXT
CS
8
6
R6
100 ?
C5
1nF
1
M1
R CS
33m ?
2
2
2
D1
R2
681k ?
R4
470 ?
C3
100pF
R1
174k ?
C2
100 μ F
Sanyo
100MV100AX
OUT1
-24V
C1
330 μ F
Sanyo
35MV330AX
R OSC
200k ?
FB
5
3 GND
R3
5.11k ?
C FB
1nF
7
PGND
REF
4
C REF
2.2 μ F
D1, D2: Central Semiconductor CMR1U-02
M1: International Rectifier IRLL2705
T1: Coiltronics CTX01-14853
*INPUT RANGE LIMITED BY OUTPUT POWER REQUIREMENTS.
SEE MAXIMUM OUTPUT POWER AND TYPICAL OPERATING CHARACTERISTICS .
Figure 1. Standard Application Circuit
Low-Dropout Regulator (LDO)
All MAX1856 functions, including EXT, are internally
powered from the on-chip, low-dropout 5V regulator.
The regulator input is at V CC , while its output is at LDO.
The V CC -to-LDO dropout voltage is typically 200mV
(300mV max at 12mA), so that when V CC is <5.2V,
V LDO is typically V CC - 200mV. When the LDO is in
dropout, the MAX1856 still operates with V CC as low as
3V (as long as the LDO exceeds 2.7V), but with
reduced amplitude FET drive at EXT. The maximum
V CC input voltage is 28V.
LDO can supply up to 12mA to power the IC, supply
gate charge through EXT to the external FET, and sup-
ply small external loads. When driving particularly large
FETs at high switching rates, little or no LDO current
may be available for external loads. For example, when
switched at 500kHz, a large FET with 20nC gate charge
requires 20nC ? 500kHz, or 10mA.
Soft-Start
The MAX1856 features a “ digital ” soft-start that is pre-
set and requires no external capacitor. Upon startup,
the peak inductor current increments from 1/5th of the
value set by R CS , to the full current-limit value in five
steps over 1024 cycles of f OSC or f SYNC . Additionally,
the oscillator runs at 1/3 the normal operating frequen-
cy (f OSC /3) until the output voltage reaches 20% of its
nominal value (V FB ≤ 1.0V). See the Typical Operating
Characteristics for a scope picture of the soft-start
operation. Soft-start is implemented: 1) when power is
first applied to the IC, 2) when exiting shutdown with
power already applied, and 3) when exiting undervolt-
age lockout. The MAX1856 ’ s soft-start sequence does
not start until V LDO reaches 2.5V.
Design Procedure
The MAX1856 can operate within a wide input voltage
range from 3V to 28V. This allows it to be used with wall
adapters. In applications driven by low-power, low-cost
and low input and output ripple current requirements,
the MAX1856 flyback topology can be used to gener-
ate various levels of output voltages and multiple out-
puts.
Communications over the Internet interface with a stan-
dard telephone connection, which includes the
Subscriber Line Interface Circuit (SLIC). The SLIC
requires a negative power supply for the audio and
ringer functions. The circuits discussed here are
designed for these applications. The following design
discussions are related to the standard application cir-
_______________________________________________________________________________________
9
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