参数资料
型号: MAX1858
厂商: Maxim Integrated Products, Inc.
英文描述: Dual 180∑ Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and POR
中文描述: 双路、180°异相、PWM降压型控制器,带有电源顺序控制及POR
文件页数: 18/22页
文件大小: 553K
代理商: MAX1858
M
Dual 180° Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
18
______________________________________________________________________________________
At some higher frequency, the output capacitor
s
impedance becomes insignificant compared to its ESR,
and the LC system becomes more like an LR system,
turning a double pole into a single pole. This zero
occurs at:
A final pole is added using C
COMP_B
to reduce the
gain and attenuate noise after crossover. This pole
(f
COMP_B
) occurs at:
Figure 10 shows a Bode plot of the poles and zeros in
their relative locations.
Near crossover, the following approximations can be
made to simplify the loop-gain equation:
R
COMP
has much higher impedance than C
COMP
.
This is true if, and only if, crossover occurs above
f
Z_COMP_A
. If this is true, C
COMP_A
can be ignored
(as a short to ground).
R
ESR
is much higher impedance than C
OUT
. This is
true if, and only if, crossover occurs well after the out-
put capacitor
s ESR zero. If this is true, C
OUT
becomes an insignificant part of the loop gain and can
be ignored (as a short to ground).
C
COMP_B
is much higher impedance than R
COMP
and can be ignored (as an open circuit). This is true
if, and only if, crossover occurs far below f
COMP_B
.
The following loop-gain equation can be found by using
these previous approximations with Figure 9:
Setting the loop gain to 1 and solving for the crossover
frequency yields:
To ensure stability, select R
COMP
to meet the following
criteria:
Unity-gain crossover must occur below 1/5th of the
switching frequency.
For reasonable phase margin using type 1 compen-
sation, f
CO
must be larger than 5
f
ESR
.
Choose C
COMP_A
so that f
Z_COMP_A
equals half f
LC
using the following equation:
Choose C
COMP_B
so that f
COMP_B
occurs at 3 times
f
CO
using the following equation:
C
f
R
COMP B
CO
COMP
_
=
×
×
(
)
×
1
2
3
π
C
LC
R
COMP A
OUT
COMP
_
=
×
2
f
GBW
V
V
R
V
V
R
×
g
L
CO
IN
RAMP
COMP
×
2
π
SET
OUT
ESR
M COMP
_
=
=
×
×
×
A
V
V
V
V
g
R
sL
R
L
IN
RAMP
SET
OUT
M COMP
_
COMP
ESR
×
×
×
×
f
R
COMP B
COMP COMP B
_
_
=
×
1
2
π
f
R
ESR
ESR OUT
=
×
1
2
π
COMP_
R
COMP_
C
COMP_A
C
COMP_B
g
M_COMP
P
W
M
V
C
V
SET
DH
DL
N
N
L
LX
FB
V
OUT
R
ESR
C
OUT
COMP_
R
COMP_
C
COMP_A
C
COMP_B
g
M_COMP
V
SET
L
LX
FB
R
ESR
C
OUT
GAIN = +V
IN
/V
RAMP
=
Figure 9. Fixed-Frequency Voltage-Mode Control Loop
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