参数资料
型号: MAX19192ETI+
厂商: Maxim Integrated Products
文件页数: 18/22页
文件大小: 0K
描述: IC ADC 8BIT DUAL 10MSPS 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
位数: 8
采样率(每秒): 10M
转换器数目: 2
功率耗散(最大): 1.67W
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 管件
输入数目和类型: 4 个单端,单极;2 个差分,单极
MAX19192
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Normal operating mode,
fIN = 1.875MHz at -0.5dBFS, CL
≈ 10pF
1.6
mA
Idle mode (three-state), DC input, CLK =
GND or VDD, PD0 = OVDD, PD1 = OGND
0.1
5.0
Standby mode, DC input, CLK = GND or
VDD, PD0 = OGND, PD1 = OVDD
0.1
Digital Output Supply Current
(Note 3)
IODD
Shutdown mode, CLK = GND or VDD,
PD0 = PD1 = OGND
0.1
5.0
A
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
tDOA
50% of CLK to 50% of data, Figure 5
(Note 4)
1
6
8.5
ns
CLK Fall to CHB Output Data
Valid
tDOB
50% of CLK to 50% of data, Figure 5
(Note 4)
1
6
8.5
ns
CLK Rise/Fall to A/
B Rise/Fall
Time
tDA/B
50% of CLK to 50% of A/
B, Figure 5
(Note 4)
1
6
8.5
ns
PD1 Rise to Output Enable
tEN
PD0 = OVDD
5ns
PD1 Fall to Output Disable
tDIS
PD0 = OVDD
5ns
CLK Duty Cycle
50
%
CLK Duty-Cycle Variation
±10
%
Wake-Up Time from Shutdown
Mode
tWAKE, SD (Note 5)
20
s
Wake-Up Time from Standby
Mode
tWAKE, ST (Note 5)
5.5
s
Digital Output Rise/Fall Time
20% to 80%
2
ns
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
fIN,X = 1.875MHz at -0.5dBFS,
fIN,Y = 3.0MHz at -0.5dBFS
-75
dB
Amplitude Matching
fIN = 1.875MHz at -0.5dBFS (Note 6)
±0.03
dB
Phase Matching
fIN = 1.875MHz at -0.5dBFS (Note 6)
±0.03
Degrees
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL
≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM =
0.33F, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
_______________________________________________________________________________________
5
Note 1: Specifications
≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3: The power consumption of the output driver is proportional to the load capacitance (CL).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: SINAD settles to within 0.5dB of its typical value.
Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
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