参数资料
型号: MAX192BEWP+
厂商: Maxim Integrated Products
文件页数: 5/24页
文件大小: 0K
描述: IC ADC 10BIT SERIAL 20-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 36
类型: 数据采集系统(DAS),ADC
分辨率(位): 10 b
采样率(每秒): 133k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
电压电源: 单电源
电源电压: ±5V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC W
包装: 管件
产品目录页面: 1393 (CN2011-ZH PDF)
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX192. Figure 11b shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
__________ Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry will activate the
MAX192 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have been sta-
bilized, the internal reset time is 100s and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT will shift out zeros.
Reference-Buffer Compensation
In addition to its shutdown function, the SHDN pin also
selects internal or external compensation. The compen-
sation affects both power-up time and maximum conver-
sion speed. Compensated or not, the minimum clock
rate is 100kHz due to droop on the sample-and-hold.
To select external compensation, float SHDN. See the
Typical Operating Circuit, which uses a 4.7F capacitor
at VREF. A value of 4.7F or greater ensures stability
and allows operation of the converter at the full clock
speed of 2MHz. External compensation increases
power-up time (see the
Choosing Power-Down Mode
section, and Table 5).
Internal compensation requires no external capacitor at
VREF, and is selected by pulling SHDN high. Internal
compensation allows for shortest power-up times, but is
only available using an external clock and reduces the
maximum clock rate to 400kHz.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________
13
tSDV
tSSTRB
PD0 CLOCKED IN
tSTR
SSTRB
SCLK
CS
tSSTRB
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
18
20
24
START SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
B9
MSB
B8
B7
B0
LSB
S1
S0
ACQUISITION
1.5s (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
10s MAX
A/D STATE
2
3
5
6
7
9
10
11
19
21
22
23
tCONV
Figure 8. External Clock Mode SSTRB Detailed Timing
Figure 9. Internal Clock Mode Timing
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