参数资料
型号: MAX195BEWE+T
厂商: Maxim Integrated Products
文件页数: 28/28页
文件大小: 0K
描述: IC ADC 16BIT 85KSPS 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
位数: 16
采样率(每秒): 85k
数据接口: QSPI?,串行,SPI?
转换器数目: 2
功率耗散(最大): 80mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极;1 个单端,双极
If you read the data bits between conversions, you can:
1) count CLK cycles until the end of the conversion, or
2) poll EOC to determine when the conversion is
finished, or
3) generate an interrupt on EOC’s falling edge.
Note that the MSB conversion result appears at DOUT
after CS goes low, but before the first SCLK pulse.
Each subsequent SCLK pulse shifts out the next con-
version bit. The 15th SCLK pulse shifts out the LSB.
Additional clock pulses shift out zeros.
MAX195
16-Bit, 85ksps ADC with 10A Shutdown
_______________________________________________________________________________________
9
CLK
START
CONV
MAX195
CONV
START
CLK
SEE
DIGITAL INTERFACE SECTION
CS
CONV
CLK
(CASE 1)
CLK
(CASE 2)
EOC
tDV
tCD
tCW
tCEH
CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE
tCEL
DOUT
tDH
B15
CONVERSION
BEGINS
CONVERSION
ENDS
MSB
LSB
B14
B13
B12
B2
B1
B0
B15
B15 FROM PREVIOUS
CONVERSION
Figure 5. Gating CONV to Synchronize with CLK
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
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